J.Miyakoshi presented at VLSI-SoC 2006 held in France.

D3 J.Miyakoshi announced at International Conference IFIP VLSI – SoC 2006 held in Nice, France from 16 – 18 October 2006.

• J. Miyakoshi, Y. Murachi, T. Matsuno, M. Hamamoto, T. Iinuma, T. Ishihara, H. Kawaguchi, and M. Yoshimoto, “A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing,” Proc. 14th IFIP International Conference on Very Large Scale Integration (VLSI-SoC 2006), pp.192-197, Nice, France, Oct. 2006.