With the advancement of high performance of information terminals such as mobile terminals, integrated circuits (LSI) mounted on them have been increasingly scaled up. According to the Semiconductor Technology Roadmap (ITRS), the memory capacity of the processor is expected to be twelve times over the next ten years. However, increasing the memory capacity will increase power consumption, which will directly lead to a reduction in continuous operation time in mobile terminals and others. For this reason, power consumption of memory is a big problem in advancing the scale-up of LSI in the future. Therefore, our RAM project team is conducting R & D on low power consumption and highly reliable memory design technology.
In this project we will propose micro architecture · circuit · design technology aiming for high reliability and low power consumption of memory.Currently, memory called SRAM (Static Random Access Memory) is used for many processors. This memory has many advantages such as high speed, low power consumption, simple peripheral circuitry, easy integration with logic operation circuit. However, memory power consumption has increased due to increased performance variations of transistors due to miniaturization of technology nodes, and increased capacity of SRAMs and poor yields. In order to solve this problem, our project is roughly divided into two projects.
Research on circuit design technology of nonvolatile memory
Currently, many system LSIs are equipped with SRAM as a memory for storing processing data. However, SRAM is called volatile memory and can not hold stored data because it can not hold stored data when there is no voltage supply from the power supply. For systems that are always on, the power efficiency is degraded for applications with low active rates and long standby times, such as sensor networks, mobile information devices, and healthcare devices. Therefore, a normally off system has been devised in which the power is turned on only during operation, and the power is turned off when in standby mode. The normally-off system is equipped with a nonvolatile memory that can keep holding the stored data even when there is no voltage supply, and can turn off the power by writing the stored data in this memory at standby . We are conducting research on two kinds of nonvolatile memories.
Low power consumption circuit technology research on ferroelectric memory (FeRAM: Ferroelectric RAM)
FeRAM is a nonvolatile memory using a ferroelectric capacitor. This ferroelectric capacitor is a dielectric that changes the direction of polarization (a state in which electric positive / negative occurs in a substance) by applying a voltage and can maintain its polarization direction even when power supply stops. Utilizing this nonvolatility characteristic, it is used as a smart card or battery-free memory.
In this research, we aim at low power consumption of 6T4C FeRAM with four ferroelectric capacitors connected to the internal node of 6T memory cell. This memory can operate at high speed like SRAM, and since the ferroelectric capacitor’s nonvolatility makes it possible to shut off the power supply during sleep, the leakage current at sleep can be reduced to zero. 6T4C FeRAM with such excellent features, but there are problems as well. One is that the power consumption increases along with the capacity of the internal node by the added ferroelectric capacitor. The other is to consume power at sleep start and return from sleep state. In this project, in order to realize low power consumption in the normally off system, we are researching and developing methods to reduce these two power consumption.
Research on low voltage circuit technology of magnetoresistive random access memory (MRAM: Magnetoresistive RAM)
MRAM is a nonvolatile memory using a magnetic change device having a characteristic that the resistance value varies according to the direction of magnetization. This magnetic change device is composed of three layers: a fixed layer whose direction of magnetization does not change, a free layer whose magnetization direction changes, and a tunnel insulating film, and changes the magnetization direction of the free layer by current. The resistance value of the magnetic change device varies depending on the direction of magnetization of the free layer, and 0/1 of data is judged by the magnitude of its resistance value. The feature of this MRAM is that it can be rewritten infinitely.
In this research, we aim to lower the voltage of MRAM cells composed of one magnetic change device and one transistor. Besides nonvolatile memories, this memory has the advantage of high integration because it has a smaller area than SRAM. However, this memory has two problems at low voltage operation. One is that the writing speed is significantly slower than reading. The other is to read out depending on the difference in resistance of the magnetic change device, so the 0/1 voltage difference is small at low voltage operation and reading is difficult. In this project, we are researching and developing a method to solve the problem of reading and writing at low voltage operation.
Research on circuit design technology for high reliability, low power consumption memory
In the conventional SRAM memory, it consists of six transistor (6T) memory cells mainly using a transistor called a MOSFET.
7 transistors / 14 transistors (7T / 14T) dependable memory and applied technology
In this research, by connecting two internal nodes of 6T memory cell, we realized high reliability, data copy function in bulk, and batch data comparison function in bulk. In general, 1-bit data is stored in one memory cell, but in the proposed 14 T cell, by recording 1 bit data in 2 cells, high reliability is achieved for 1 bit of data I will. In addition, we propose a mechanism for copying and comparing data between memory cell pairs, realizing high speed and low energy in applications such as transactional memory and redundancy circuit.
Design of low power 8T 3 port SRAM for image processing processor using 28-nm FD-SOI
In this research, we propose low voltage / low power multiport SRAM technology suitable for image processor. The proposed SRAM technology consists of 8 transistor bit cells and has 3 ports of 1-writing / 2-reading that can be accessed at the same time. This proposed SRAM realizes SRAM circuit of smaller area than conventional 3-port SRAM circuit, and at the same time, by providing majority logic circuit technology, it reduces energy during operation. The proposed technique was implemented using the 28-nm FD-SOI process and measured and evaluated. As a result, it showed that by using the proposed SRAM technology, it operates at ultralow voltage of minimum voltage 0.46 V and can operate with ultra low energy below several hundred-fJ / cycle.
8T Three-port SRAM cell design, memory array schematic, and total power consumption of motion estimation image processor.
About external results · research results
Yoshimoto Laboratory is a university educational institution with the world’s leading SRAM design and development technology. Regardless of company or university, we collaborate with many collaborative researchers and make technical suggestions diversely. In addition, it has received high praise, such as adopting three of the world’s highest class semiconductors related to the VLSI Symposium of the world’s highest class (approval rate of about 25%) in the past six years.