Journal Papers

2019

  1. Masahiko Yoshimoto and Shintaro Izumi, “Recent progress of biomedical processor SoC for wearable healthcare application: A Review”, iEICE Vol.E102-C, No.4, pp.245-259, 2019
  2. Seiya Yoshida, Shintaro Izumi, Koichi Kajihara, Yuji Yano, Hiroshi Kawaguchi, and Masahiko Yoshimoto, “Energy-Efficient Spectral Analysis Method Using Autoregressive Model-Based Approach for Internet of Things,” IEEE Transaction on Circuit and Systems I: Regular Papers, volume:66, Issue:10, pp.3896-3950, Oct. 2019.

2018

  1. Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi and Masahiko Yoshimoto, “A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme,” IEEE Trans. on Circuits and Systems I Reg. Papers, Vol. -, No. -, pp.1-12, Dec. 2018. (Early Access)
  2. Motofumi Nakanishi, Shintaro Izumi, Sho Nagayoshi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Toshikazu Shiga, Takafumi Ando,  Satoshi Nakae, Chiyoko Usui, Tomoko Aoyama and Shigeho Tanaka,” Estimating metabolic equivalents for activities in daily life using acceleration and heart rate in wearable devices,” BioMedical Engineering OnLine, Vol. 17, No. 1, pp.100-, July. 2018.
  3. Motofumi Nakanishi, Shintaro Izumi, Mio Tsukahara, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori and Masahiko Yoshimoto,” A 11.3-µA Physical Activity Monitoring System Using Acceleration and Heart Rate,” IEICE Transactions on Electronics, E101.C, No. 4, pp.233-242, April. 2018.
  4. Takaaki Okano, Shintaro Izumi, Takumi Katsuura, Hiroshi Kawaguchi, Masahiko Yoshimoto,” Multimodal Cardiovascular Information Monitor Using Piezoelectric Transducers for Wearable Healthcare,”Journal of Signal Processing Systems, pp.1-10, Dec.2018.

2017

  1. Go Matsukawa, Taisuke Kodama, Yuri Nishizumi, Koichi Kajihara, Chikako Nakanishi, Shintaro Izumi, Hiroshi Kawaguchi, Toshio Goto, Takeo Kato and Masahiko Yoshimoto,” A low power, VLSI object recognition processor using Sparse FIND Feature for 60fps HDTV resolution video,” IEICE Electronics Express, Vol. 14, No. 15, pp.1-12, July. 2017.
  2. Y. Umeki, S. Izumi, H. Kitahara, T. Nakagawa, K. Yanagida, S. Yoshimoto, H.Kawaguchi, M. Yoshimoto, H. Kimura, K. Marumoto, T. Fuchikami, and Y.Fujimori, “A Novel Test Scheme for Detecting Faulty Recall Margin Cells for 6T-4C FeRAM,” Memoirs of the Graduate Schools of Engineering and System Informatics Kobe University, no. 8, pp. 5-8, Feb. 2017.

2016

  1. H. Mori, Y. Umeki, S. Yoshimoto, S. Izumi, K. Nii, H. Kawaguchi and M. Yoshimoto, “A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor,” IEICE Trans. Electron., Vol.E99-C, No.8, pp.901-908, Aug. 2016.
  2. Y. Umeki, K. Yanagida, S. Yoshimoto, S. Izumi, M. Yoshimoto, H. Kawaguchi, K. Tsunoda, and T. Sugii, “A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM,” IPSJ Transactions on System LSI Design Methodology (TSLDM), vol. 9, pp. 79-83, Aug. 2016.
  3. Go Matsukawa, Yuta Kimi, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, and Masahiko Yoshimoto, “Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-convergent Path,” IEICE Trans. Electron., Vol.E99-A, No.6, pp.1198-1205, Jun. 2016.

2015

  1. K. Okuno, S. Izumi, K. Masaki, H. Kawaguchi, and M. Yoshimoto, “A Fast Settling All Digital PLL using Temperature Compensated Oscillator Tuning Word Estimation Algorithm,” IEICE Trans. Fundamentals., Vol.E98-A, No.12, pp.2590-2597, Dec. 2015.
  2. S. Izumi, K. Yamashita, M. Nakano, H. Kawaguchi, H. Kimura, K. Marumoto, T. Fuchikami, Y. Fujimori, H. Nakajima, T. Shiga, and M. Yoshimoto, “A Wearable Healthcare System with a 13.7 μA Noise Tolerant ECG Processor,” IEEE Transactions on Biomedical Circuits and Systems, vol.9, no.5, pp.733-742, Oct. 2015. doi: 10.1109/TBCAS.2014.2362307.
  3. S. Izumi, K. Yamashita, M. Nakano, S. Yoshimoto, T. Nakagawa, Y. Nakai, H. Kawaguchi, H. Kimura, K. Marumoto, T. Fuchikami, Y. Fujimori, H. Nakajima, T. Shiga, and M. Yoshimoto, “Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector,” IEEE Transactions on Biomedical Circuits and Systems, vol.9, no.5, pp.641-651, Oct. 2015. doi: 10.1109/TBCAS.2015.2452906.
  4. K. Okuno, T. Konishi, S. Izumi, M. Yoshimoto and H. Kawaguchi, “Low-Jitter Design for Second-Order Time-to-Digital Converter Using Frequency Shift Oscillators,” IEICE Trans. Fundamentals, Vol.E98-A, No.7, pp.1475-1481, Jul. 2015.
  5. K. Okuno, T. Konishi, S. Izumi, M. Yoshimoto and H. Kawaguchi, “An I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter,” IEICE Trans. Electron., Vol.E98-C, No.6, pp.489-495, Jun. 2015.
  6. S. Izumi, M. Nakano, K. Yamashita, Y. Nakai, H. Kawaguchi, and M. Yoshimoto, “Noise Tolerant Heart Rate Extraction Algorithm Using Short-Term Autocorrelation for Wearable Healthcare Systems,” IEICE Transactions on Information and Systems, Vol.E98-D, No.5, pp.1095-1103, May 2015.
  7. G. Matsukawa, Y. Nakata, Y. Sugure, S. Oho, Y. Kimi, M. Shimozawa, S. Yoshida, H. Kawaguchi and M. Yoshimoto, “A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme,” IEICE Trans. Electron., Vol.E98-C, No.4, pp.333-339, Apr. 2015.

2014

  1. Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii, “STT-MRAM Operating at 0.38V Using Negative-Resistance Sense Amplifier,” IEICE Trans. Fundamentals, Vol.E97-A, No.12, pp.2411-2417, Dec. 2014.
  2. K. Takagi, K. Tanaka, S. Izumi, H. Kawaguchi and M. Yoshimoto, “A Real-time Scalable Object Detection System using Low-power HOG Accelerator VLSI,” Journal of Signal Processing Systems, Vol. 76, Issue 3, pp. 261-274, Sep. 2014.
  3. S. Yoshimoto, H. Kawaguchi and M. Yoshimoto, “Soft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell,” IEICE Trans. Fundamentals, Vol. E97-A, No. 9, pp. 1945-1951, Sep. 2014.
  4. Y. Nakata, Y. Kimi, S. Okumura, J. Jung, T. Sawada, T. Toshikawa, M. Nagata, H. Nakano, M. Yabuuchi, H. Fujiwara, K. Nii, H. Kawai, H. Kawaguchi and M. Yoshimoto, “A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation,” IEICE Trans. Electron., Vol. E97-C, No. 4, pp. 332-341, Apr. 2014.
  5. G. He, Y. Miyamoto, K. Matsuda, S. Izumi, H. Kawaguchi, and M. Yoshimoto, “A 54-mW 3x-Real-Time 60-kWord Continuous Speech Recognition Processor VLSI,” IEICE Electronics Express, Vol. 11, No. 2, pp. 1-9, Jan. 2014.

2013

  1. S. Yoshimoto, S. Okumura, K. Nii, H. Kawaguchi, and M. Yoshimoto, “Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout,” IEICE Trans. Fundamentals, Vol. E96-A, No. 7, pp. 1579-1585, July 2013.
  2. J. Jung, Y. Nakata, S. Okumura, H. Kawaguchi, and M. Yoshimoto, “Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM,” IEICE Trans. Electron., Vol. E96-C, No. 4, pp. 528-537, Apr. 2013.
  3. G. He, T. Sugahara, Y. Miyamoto, S. Izumi, H. Kawaguchi, and M. Yoshimoto, “A 168-mW 2.4x-Real-Time 60-kWord Continuous Speech Recongnition Processor VLSI,” IEICE Trans. Electron., Vol. E96-C, No. 4, pp. 444-453, Apr. 2013.
  4. K. Mizuno, K. Takagi, Y. Terauchi, S. Izumi, H. Kawaguchi, and M. Yoshimoto, “A sub-100 mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video,” IEICE Trans. Electron., Vol. E96-C, No. 4, pp. 433-443, Apr. 2013.
  5. T. Konishi, K. Okuno, S. Izumi, M. Yoshimoto, and H. Kawaguchi, “A second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops,” IEICE Trans. Electron., Vol. E96-C, No. 4, pp.546-552, Apr. 2013.

2012

  1. S. Okumura, S. Yoshimoto, H. Kawaguchi, and M. Yoshimoto, “A 128-bit Chip Identification Generating Scheme Exploiting Load Transistor’s Variation in SRAM Bitcells,” IEICE Trans. Fundamentals, Vol. E95-A, No. 12, pp. 2226-2233, Dec. 2012.
  2. S. Yoshimoto, T. Amashita, S. Okumura, H Kawaguchi, and M. Yoshimoto, “Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure,” IEICE Trans. Electron., Vol. E95-C, No. 10, pp. 1675-1681, Oct. 2012.
  3. G. He, T. Sugahara, T. Fujinaga, Y. Miyamoto, H. Noguchi, S. Izumi, H. Kawaguchi, and M. Yoshimoto, ” A 40 nm 144 mW VLSI Processor for Realtime 60 kWord Continuous Speech Recognition,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 8, pp.1656-1666, Aug. 2012.
  4. S. Yoshimoto, M. Terada, S. Okumura, T. Suzuki, S. Miyano, H. Kawaguchi, and M. Yoshimoto “A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique,” IEICE Electronics Express, Vol. 9, No. 12, pp. 1023-1029, June 2012.
  5. S. Yoshimoto, T. Amashita, S. Okumura, K. Nii, M. Yoshimoto, and H. Kawaguch, “Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process,” IEICE Trans. Fundamentals, Vol. E95-A, No. 8, pp. 1359-1365, Aug. 2012.
  6. S. Okumura, H. Fujiwara, K. Yamaguchi, S. Yoshimoto, M. Yoshimoto, and H. Kawaguchi, “A 0.15-μm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme,” IEICE Trans. Electron., Vol. E95-C, No. 4, pp. 579-585, Apr. 2012.
  7. S. Yoshimoto, M. Terada, S. Okumura, T. Suzuki, S. Miyano, H. Kawaguchi, and M. Yoshimoto, “A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme,” IEICE Trans. Electron., Vol. E95-C, No. 4, pp. 572-578, Apr. 2012.
  8. Y. Nakata, H. Kawaguchi, and M. Yoshimoto, “A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing,” IEICE Trans. Electron., Vol. E95-C, No. 4, pp. 523-533, Apr. 2012.
  9. S. Okumura, Y. Nakata, K. Yanagida, Y. Kagiyama, S. Yoshimoto, H. Kawaguchi, M. Yoshimoto, “Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy,” IEICE Electronics Express, Vol. 9, No. 6, pp.470-476, March, 2012.
  10. Y. Nakata, S. Okumura, H. Kawaguchi, and M. Yoshimoto, “0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme,” IPSJ Transactions on System LSI Design Methodology, vol. 5, pp.32-43. Feb. 2012.
  11. T. Matsuda, S. Izumi, Y. Sakai, T. Takeuchi, H. Fujiwara, H. Kawaguchi, C. Ohta, and M. Yoshimoto, “Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes,” IEICE Transactions on Communications, vol. E95-B, no. 1, pp. 178-188, Jan. 2012.

2011

  1. S. Okumura, Y. Kagiyama, Y. Nakata, S. Yoshimoto, H. Kawaguchi, and M. Yoshimoto, “7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory,” IEICE Trans. Fundamentals, vol. E94-A, No. 12, pp. 2693-2700, Dec. 2011.
  2. T. Konishi, H. Lee, S. Izumi, T. Takeuchi, M. Yoshimoto, H. Kawaguchi, “A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E94-A, No.12, pp.2701-2708, Dec. 2011.
  3. T. Konishi, S. Izumi, K. Tsuruda, H. Lee, T. Takeuchi, M. Yoshimoto, H. Kawaguchi, “A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E94-A, No.11, pp.2287-2294, Nov. 2011.
  4. H. Noguchi, K. Miura, T. Fujinaga, T. Sugahara, H. Kawaguchi, and M. Yoshimoto, “VLSI Architecture of GMM Processing and Viterbi Decoder for 60,000-Word Real-Time Continuous Speech Recognition,” IEICE Trans. Electron., vol. E94-C, no. 4, pp. 458-467, Apr. 2011.
  5. K. Mizuno, H. Noguchi, G. He, Y. Terachi, T. Kamino, T. Fujinaga, S. Izumi, Y. Ariki, H. Kawaguchi and M. Yoshimoto, “A Low-power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition,” IEICE Trans. Electron., vol. E94-C, no. 4, pp. 448-457, Apr. 2011.
  6. H. Noguchi, T. Takagi, K. Kugata, S. Izumi, M. Yoshimoto, and H. Kawaguchi, “Data-Intensive Sound Acquisition System with Large-Scale Microphone Array,” Journal of Information Processing Society of Japan (IPSJ), vol. 19, Mar. 2011.
  7. H. Noguchi, Y. Iguchi, H. Fujiwara, S. Okumura, K. Nii, H. Kawaguchi, and M. Yoshimoto, “Design Choice in 45-nm Dual-Port SRAM – 8T, 10T Single End, and 10T Differential –,” IPSJ Transactions on System LSI Design Methodology, vol. 4, pp. 80-90, Feb. 2011.

2010

  1. S. Izumi, T. Takeuchi, T. Matsuda, H. Lee, T. Konishi, K. Tsuruda, Y.Sakai, H. Kawaguchi, C. Ohta, and M. Yoshimoto, “A 58-uW Single-Chip Sensor Node Processor with Communication Centric Design,” IEICE Transactions on Electronics, vol. E93-C, no. 3, pp.261-269, Mar. 2010.
  2. Takashi Matsuda, Takashi Takeuchi, Takefumi Aonishi, Masumi Ichien, Hiroshi Kawaguchi, Chikara Ohta and Masahiko Yoshimoto, “A power-variation model for sensor node and the impact against life time of wireless sensor networks” , IEICE Electron. Express, Vol. 7, No. 3, pp.197-202, 2010.

2009

  1. T. Takeuchi, S. Mikami, H. Lee, H. Kawaguchi, C. Ohta, and M. Yoshimoto, “A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks, ” IEICE Transactions on Communications, vol. E92-C, no. 6, pp. 815-821, June 2009.
  2. H. Fujiwara, S. Okumura, Y. Iguchi, H. Noguchi, H. Kawaguchi, and M. Yoshimoto, “A Dependable SRAM with 7T/14T Memory Cells,” IEICE Transactions on Electronics, vol. E92-C, no. 4, pp. 423-432, Apr. 2009.

2008

  1. T. Takeuchi, Y. Otake, M. Ichien, A. Gion, H. Kawaguchi, C. Ohta, and M. Yoshimoto, “Cross-Layer Design for Low-Power Wireless Sensor Node Using Wave Clock, ” IEICE Transactions on Communications, vol. E91-B, no. 11, pp. 3480-3488, Nov. 2008.
  2. S. Izumi, T. Takeuchi, T. Matsuda, H. Kawaguchi, C. Ohta, and M. Yoshimoto, “Counter-based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks,” IEICE Transactions on Communications, vol. E91-B, no. 11, pp. 3489-3498, Nov. 2008.
  3. Y. Murachi, J. Miyakoshi, M. Hamamoto, T. Iinuma, T. Ishihara, F. Yin, J. Lee, H. Kawaguchi, and M. Yoshimoto, “A sub 100 mW H.264 MP@L4.1 Integer-pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-connected Systolic Array and Segmentation-free, Rectangle-access Search-window Buffer,” IEICE Trans. Electron., April 2008.
  4. Y. Murachi, Y. Fukuyama, R. Yamamoto, J. Miyakoshi, H. Kawaguchi, H. Ishihara, M. Miyama, Y. Matsuda and M. Yoshimoto, “A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition,” IEICE Trans. Electron., April 2008.
  5. H. Noguchi, Y. Iguchi, H. Fujiwara, S. Okumura, Y. Morita, K. Nii, H. Kawaguchi, and M. Yoshimoto, “A 10T Non-Precharge Two-Port SRAM Reducing Readout Power for Video Processing,” IEICE Trans. Electron., vol. E91-C, no. 4, pp. 543-552, April 2008.
  6. H. Fujiwara, K. Nii, H. Noguchi, J. Miyakoshi, Y. Murachi, Y. Morita, H. Kawaguchi, and Masahiko Yoshimoto, “Novel Video Memory Reduces 45% of Bitline Power using Majority Logic and Data-Bit Reordering,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 6, pp. 620-627, June 2008.

2007

  1. T. Matsuda, M. Ichien, H. Kawaguchi, C. Ohta, and M. Yoshimoto, “Data Transmission Scheduling based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks,” IEICE Trans. Communications, vol.E90-B, vol.12, pp.3410-3418, Dec. 2007.
  2. Y. Morita, H. Fujiwara, H. Noguchi, Y. Iguchi, K. Nii, H. Kawaguchi, and M. Yoshimoto, “Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme,” IEICE Trans. Fundamentals, vol. E90-A, No. 12, pp. 2695-2702, Dec. 2007.
  3. Y. Morita, H. Fujiwara, H. Noguchi, Y. Iguchi, K. Nii, H. Kawaguchi, and M. Yoshimoto, “Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes,” IEICE Trans. Electron., vol.E90-C, No.10, pp.1949-1956, Oct. 2007.

2006

  1. J. Miyakoshi, Y. Murachi, T. Matsuno, M. Hamamoto, T. Iinuma, T. Ishihara, H. Kawaguchi, M. Miyama and M. Yoshimoto, “A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture,” IEICE Trans. Fundamentals, Vol.E89-A, No.12, pp.3623-3633, Dec. 2006.
  2. Y. Morita, H. Fujiwara, H. Noguchi, K. Kawakami, J Miyakoshi, S. Mikami, K. Nii, H. Kawaguchi, and M. Yoshimoto, “A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond,” IEICE Trans. Fundamentals, Vol.E89-A, No.12, pp.3634-3641, Dec. 2006.
  3. K. Kawakami, J. Takemura, M. Kuroda, H. Kawaguchi, and M. Yoshimoto, “A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline,” IEICE Trans. Fundamentals, Vol.E89-A, No.12, pp.3642-3651, Dec. 2006.
  4. J. Miyakoshi, Y. Murachi, T. Ishihara, H. Kawaguchi, and M. Yoshimoto, “A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing,” IEICE Trans. Electronics, Vol.E89-C, No.11, pp.1629-1636, Nov. 2006.
  5. S. Mikami, T. Aonishi, H. Yoshino, C. Ohta, H. Kawaguchi, and M. Yoshimoto, “Aggregation Efficient-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks,” IEICE Trans. Communications, Vol.E89-B, No.10, pp.2741-2751, Oct. 2006.
  6. K. Kawakami, M. Kanamori, Y. Morita, J. Takemura, H. Ohira, M. Miyama, M. Yoshimoto, “A Feed-Forward Dynamic VDD-VBB-Frequency Management for Low Power Motion Video Compression on 90nm RISC Processor,” Intelligent Automation and Soft Computing (AutoSoft? Journal), Vol.12, No.3, pp.283-298, 2006.
  7. S. Mikami, T. Matsuno, M. Miyama, H. Kawaguchi, M. Yoshimoto, and H. Ono,, “An Energy-Harvesting Wireless-Interface SoC for Short-Range Data Communication,” IEEJ Trans. Electronics, Information and Systems, Vol.126, No.5, pp.565-570, May 2006.
  8. N. Minegishi, J. Miyakoshi, Y. Kuroda, T. Katagiri, Y. Fukuyama, R. Yamamoto, M. Miyama, K. Imamura, H. Hashimoto, and M. Yoshimoto, “VLSI Architecture Study of a Read-Time Scalable Optical Flow Processor for Video Segmentation,” IEICE Trans. Electronics, Vol.E89-C, No.3, pp.230-242, March 2006.

2005

  1. K. Kawakami, M. Kanamori, Y. Morita, J. Takemura, M. Miyama, and M. Yoshimoto, “Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-dominant Technology Era,” IEICE Trans. Fundamentals, Vol.E88-A, No.12, pp.3290-3297, Dec. 2005.
  2. Y. Murachi, K. Hamano, T. Matsuno, J. Miyakoshi, M. Miyama, and M. Yoshimoto, “A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application,” IEICE Trans. Fundamentals, Vol.E88-A, No.12, pp.3492-3499, Dec. 2005.
  3. J. Miyakoshi, Y. Murachi, K. Hamano, T. Matsuno, M. Miyama and M. Yoshimoto, “A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation,” IEICE Trans. Electoronics, Vol.E88-C, No.4, pp.559-569, April 2005.

2004

  1. M. Miyama, J. Miyakoshi, Y. Kuroda, K. Imamura, H. Hashimoto, and M. Yoshimoto, “A sub-mW MPEG-4 motion estimation processor core for mobile video application,” IEEE J. Solid-State Circuits, Vol.39, No.9, pp.1562-1570, Sep. 2004.
  2. H. Ohira, K. Kawakami, M. Kanamori, Y. Morita, M. Miyama, and M. Yoshimoto, “A Feed-Forward Dynamic Voltage Control Algorithm for Low Power MPEG4 on Multi-Regulated Voltage CPU,” IEICE Trans. Electron., Vol.E87-C, No.4, pp.457-465, April 2004.
  3. M. Miyama, J. Miyakoshi, K. Imamura, H. Hashimoto, and M. Yoshimoto, “VLSI-Oriented Motion Estimation Using a Steepest Descent Method in Mobile Video Coding,” IEICE Trans. Electron., Vol.E87-C, No.4, pp.466-474, April 2004.

2003

  1. M. Miyama, O. Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, J. Miyakoshi, H. Hashimoto, S. Komatsu, M. Yagi, K. Taki, and M. Yoshimoto, “An Ultra Low Power Motion Estimation Processor for MPEG2 HDTV Resolution Video,” IEICE Trans. Electron., Vol.E86-C, No.4, pp.561-569, April 2003.