国際学会

2019

  1. Seiya Yoshida, Shintaro Izumi, Yuki Nishikawa, Kento Watanabe, Kana Sasai, Yuji Yano, Hiroshi Kawaguchi, and Masahiko Yoshimoto, “A Heartbeat Interval Error Compensation Method Using Multiple Linerar Regression for Photoplethysmography Sensors,” IEEE Biomedical Circuits and Systems Conference, Nara, Japan, Oct. 17-19, 2019.
  2. Kana Sasai, Shintaro Izumi, Kento Watanabe, Yuji Yano, Hiroshi Kawaguchi, and Masahiko Yoshimoto, “A Low-Power Photoplethysmography Sensor using Correlated Double Sampling and Reference Readout Circuit,” IEEE SENSORS, Montreal, Canada, Oct.27-30, 2019.

2018

  1. Yuki Miyauchi, Haruki Mori, Tetsuya Youkawa, Kazuki Yamada, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, and Atsuki Inoue, “Layer Skip Learning using LARS variables for 39% Faster Conversion Time and Lower Bandwidth,” IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 673-676, Dec. 2018
  2. Haruki Mori, Shintaro Izumi, Hiroshi Kawaguchi, and Masahiko Yoshimoto, “28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep Learning,” IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 161–164, Dec. 2018.
  3. Tetsuya Youkawa, Haruki Mori, Yuki Miyauchi, Kazuki Yamada, Shintaro Izumi, Masahiko Yoshimoto, and Hiroshi Kawaguchi, “DELAYED WEIGHT UPDATE FOR FASTER CONVERGENCE IN DATA-PARALLEL DEEP LEARNING” IEEE Global Conference on Signal and Information Processing, Anaheim, California, USA, 26–29 November 2018
  4. Koichi Kajihara, Shintaro Izumi, Seiya Yoshida, Yuji Yano, Hiroshi Kawaguchi and Masahiko Yoshimoto “Hardware Implementation of Autoregressive Model Estimation Using Burg’s Method for Low-Energy Spectral Analysis” IEEE International Workshop on Signal Processing Systems, Capetown, South Africa, 21-24 October 2018
  5. Kazuki Yamada, Haruki Mori, Tetsuya Youkawa, Yuki Miyauchi, Shintaro Izumi, Masahiko Yoshimoto and Hiroshi Kawaguchi “Adaptive Learning Rate Adjustment with Short-Term Pre-Training in Data Parallel Deep Learning” IEEE International Workshop on Signal Processing Systems, Capetown, South Africa, 21-24 October 2018
  6. Kento Watanabe, Shintaro Izumi, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto, “A 5-ms Error, 22µA Photoplethysmography Sensor using Current Integration Circuit and Correlated Double Sampling”  The 40th International Engineering in Medicine and Biology Conference, July, 2018
  7. Yuki Nishikawa, Shintaro Izumi, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto, “Sampling Rate Reduction for Wearable Heart Rate Variability Monitoring” IEEE International Symposium on Circuits & Systems, Florence, Italy, May 27-30, 2018

2017

  1. Motofumi Nakanishi, Shintaro Izumi, Mio Tsukahara, Hiroshi Kawaguchi, Masahiko Yoshimoto, “A Metabolic Equivalents Estimation Algorithm using Triaxial Accelerometer and Adaptive Sampling for Wearable Devices” The 1st IEEE Life Sciences Conference, Sydney, Australia, 13-15 Dec 2017
  2. T. Katsuura, S. Izumi, S. Yoshimoto, T. Sekitani, M. Yoshimoto, and H. Kawaguchi, “Wearable Pulse Wave Velocity Sensor Using Flexible Piezoelectric Film Array,” Proc. of IEEE Biomedical Circuits and Systems Conference (BioCAS), pp. 721–724, Oct. 2017.
  3. Yuki Nagasato, Shintaro Izumi, Hiroshi Kawaguchi,and Masahiko Yoshimoto, “Capacitively Coupled ECG Sensor System with Digitally Assisted Noise Cancellation for Wearable Application”, The 13th IEEE BioMedical Circuits and Systems Conference(BioCAS), pp.400-403, Oct. 2017.
  4. Takaaki Okano, Shintaro Izumi, Hiroshi Kawaguchi,and Masahiko Yoshimoto, “Non-Contact Biometric Identification and Authentication Using Microwave Doppler Sensor”, The 13th IEEE BioMedical Circuits and Systems Conference(BioCAS), pp.392-395, Oct. 2017.
  5. Yuri Nishizumi, Go Matsukawa, Koichi Kajihara, Taisuke Kodama, Shintaro Izumi, Hiroshi Kawaguchi, Chikako Nakanishi, Toshio Goto, Takeo Kato and Masahiko Yoshimoto, “FPGA Implementation of Object Recognition Processor for HDTV Resolution Video Using Sparse FIND Feature” IEEE Workshop on Signal Processing Systems (SiPS), Oct. 2017.
  6. Takaaki Okano, Shintaro Izumi, Takumi Katsuura, Hiroshi Kawaguchi, and Masahiko Yoshimoto, “Multimodal Cardiovascular Information Monitor using Piezoelectric Transducers for Wearable Healthcare” IEEE Workshop on Signal Processing Systems (SiPS), Oct. 2017.
  7. Haruki Mori, Tetsuya Youkawa, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, and Atsuki Inoue “A Layer-Block-Wise Pipeline For Memory And Bandwidth Reduction In Distributed Deep Learning,” IEEE International Workshop on Machine Learning for Signal Processing (MLSP), Sep. 2017.
  8. Masahiko Yoshimoto “A Wearable Biomedical Sensing System with Normally-off Computing Architecture”, invited to 17th INTERNATIONAL FORUM ON MPSoC, Annecy, July 2017.
  9. Shintaro Izumi, Daichi Matsunaga, Ryota Nakamura, Hiroshi Kawaguchi, Masahiko Yoshimoto”A contact-less heart rate sensor system for driver health monitoring”The 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC’17), July. 2017
  10. Ryota Nakamura, Shintaro Izumi, Hiroshi Kawaguchi, Hidetoshi Ohta, Masahiko Yoshimoto “A Swallowable Sensing Device Platform with Wireless Power Feeding and Chemical Reaction Actuator” The 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC’17), pp. 3040-3043, July. 2017
  11. Mio Tsukahara, Shintaro Izumi, Motofumi Nakanishi, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, and Masahiko Yoshimoto, “A 19-μA Metabolic Equivalents Monitoring SoC Using Adaptive Sampling, ” IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) University LSI Design Contest, pp. 37-38, Jan. 2017.

2016

  1. Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi and Masahiko Yoshimoto, “An Low-Energy 8T Dual-Port SRAM for Image Processor with Selective Sourceline Drive Scheme in 28-nm FD-SOI Process Technology,” IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp.532-535, Dec. 2016.
  2. Mio Tsukahara, Shintaro Izumi, Motofumi Nakanishi, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, and Masahiko Yoshimoto, “A 15-uA Metabolic Equivalents Monitoring System using Adaptive Acceleration Sampling and Normally Off Computing,” IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp.61-64, Dec. 2016.
  3. Daichi Matsunaga, Shintaro Izumi, Hiroshi Kawaguchi and Masahiko Yoshimto, “Non-contact instantaneous heart rate monitoring using microwave Doppler sensor and time-frequency domain analysis”, IEEE 16th International Conference on BioInformatics and BioEngineering(BIBE), pp.172-175, Nov. 2016.
  4. Tanaka Yoshito, Izumi Shintaro, Kawamoto Yuta, Kawaguchi Hiroshi, and Yoshimoto Masahiko,”Adaptive Noise Cancellation Method for Capacitively Coupled ECG Sensor using Single Insulated Electrode,” The 12th IEEE BioMedical Circuits and Systems Conference(BioCAS), pp.343-346, Oct. 2016.
  5. Masahiko Yoshimoto “A Wearable Biomedical Sensing System with Normally-off Computing Architecture and Physical Activity Classification Algorithm”, invited to International Conference on Solid State Devices and Materials (SSDM2016), Sept. 2016
  6. Ryota Nakamura, Shintaro Izumi, Hiroshi Kawaguchi, Hidetoshi Ohta, and Masahiko Yoshimoto,”Swallowable Sensing Device for Long-term Gastrointestinal Tract Monitoring,” 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society(EMBC), pp.3039-3042, Aug. 2016.
  7. Mio Tsukahara, Motofumi Nakanishi, Shintaro Izumi, Yozaburo Nakai, Hiroshi Kawaguchi, and Masahiko Yoshimoto, “Low-Power Metabolic Equivalents Estimation Algorithm Using Adaptive Acceleration Sampling,” 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society(EMBC), Aug. 2016.
  8. Shuhei Yoshida, Go Matsukawa, Shintaro Izumi, Hiroshi Kawaguchi, and Masahiko Yoshimoto,”An Soft Error Propagation Analysis Considering Logical Masking Effect on Re-convergent Path,” 22nd IEEE International Symposium on On-Line Testing and Robust System Design(IOLTS), July. 2016.
  9. Yohei Umeki, Koji Yanagida, Hiroaki Kurotsu, Hiroto Kitahara, Haruki Mori, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Shusuke Yoshimoto, Koji Tsunoda, Toshihiro Sugii, “Process variation tolerant counter base read circuit for low-voltage operating STT-MRAM”, DATE EMS Workshop, Mar. 2016.
  10. Yuta Kawamoto, Shintaro Izumi, Yoshito Tanaka, Hiroshi Kawaguchi, and Masahiko Yoshimoto, “Capacitively Coupled ECG Sensor using a Single Electrode with Adaptive Power-Line Noise Cancellation,” in Proc. of IEEE International Conference on Biomedical and Health Informatics (BHI), pp.212-215, Feb. 2016.

2015

  1. Yuta Kimi, Go Matsukawa, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, and Masahiko Yoshimoto,”Analysis of Soft Error Propagation considering Masking Effects on Re-convergent Path”,IEEE Asian Test Symposium (ATS), Nov. 2015 .
  2. S. Izumi, H. Kawaguchi, M. Yoshimoto, H. Kimura, T. Fuchikami, K. Marumoto, and Y. Fujimori, “(Invited) A Ferroelectric-Based Non-Volatile Flip-Flop for Wearable Healthcare Systems,” Proc. of IEEE Non-Volatile Memory Technology Symposium (NVMTS), pp.1-4, Oct. 2015.
  3. Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Koji Nii, Hiroshi Kawaguchi and Masahiko Yoshimoto, “A 298-fJ/writecycle 650-fJ/readcycle 8T Three-Port SRAM in 28-nm FD-SOI Process Technology for Image Processor,” IEEE Custom Integrated Circuits Conference (CICC), Sep. 2015.
  4. Taisuke Kodama, Shintaro Izumi, Kana Masaki, Hiroshi Kawaguchi, Kazusuke Maenaka, Masahiko Yoshimoto, “Large Displacement Haptic Stimulus Actuator using Piezoelectric Pump for Wearable Devices,” 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society(EMBC), pp.1172-1175 , Aug. 2015.
  5. Hidetoshi Ohta, Shintaro Izumi, and Masahiko Yoshimoto, “A moreacceptable endoluminal implantation for remotely monitoring ingestiblesensors anchored to the stomach wall,” in Proc. of 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), pp.4089-4092, Aug. 2015.
  6. Daichi Matsunaga, Keisuke Okuno, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto, “Non-contact and Noise Tolerant Heart Rate Monitoring using Microwave Doppler Sensor and Range Imagery,” 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society(EMBC), pp.6118-6121 , Aug. 2015.
  7. Motofumi Nakanishi, Shintaro Izumi, Sho Nagayoshi, Hironori Sato, Hiroshi Kawaguchi, Masahiko Yoshimoto, Takafumi Ando, Satoshi Nakae, Chiyoko Usui, Tomoko Aoyama, Shigeho Tanaka, “Physical Activity Group Classification Algorithm using Triaxial Acceleration and Heart Rate,” 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society(EMBC), pp.510-513 , Aug.2015.
  8. Yuta Kimi, Go Matsukawa, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, and Masahiko Yoshimoto,”An Accurate Soft Error Propagation Analysis Technique Considering Temporal Masking Disablement”,Proc. of IEEE International On-Line Testing (IOLTS), pp.23-25, Jul. 2015
  9. Tomoki Nakagawa, Shintaro Izumi, Koji Yanagida, Yuki Kitahara, Shusuke Yoshimoto, Yohei Umeki, Haruki Mori, Hiroto Kitahara, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, and Masahiko Yoshimoto “A Low Power 6T-4C Non-volatile Memoly using Charge Sharing and Non-precharge Techniques” IEEE International Symposium on Circuits and Systems (ISCAS), pp.2904-2907, May. 2015.
  10. Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii, “A Negative-Resistance Sense Amplifier for Low-Voltage Operating STT-MRAM” IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) University LSI Design Contest, pp. 8-9, Jan. 2015.
  11. Yozaburo Nakai, Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi, Masahiko Yoshimoto, “A 14μA ECG Processor with Noise Tolerant Heart Rate Extractor and FeRAM for Wearable Healthcare Systems” IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) University LSI Design Contest, pp. 16-17, Jan. 2015.

2014

  1. Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, and Hiroshi Kawaguchi, “An 8-bit I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter,” IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 223-226, Dec. 2014.
  2. Keisuke Okuno, Kana Masaki, Shintaro Izumi, Toshihiro Konishi, Hiroshi Kawaguchi and Masahiko Yoshimoto , “A 2.23 ps RMS Jitter 3 μs Fast Settling ADPLL using Temperature Compensation PLL Controller ,” IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 68-71, Dec. 2014.
  3. H. Kimura, T. Fuchikami, K. Marumoto, Y. Fujimori, S. Izumi, H.Kawaguchi, and M. Yoshimoto, “A 2.4 pJ Ferroelectric-Based Non-VolatileFlip-Flop with 10-Year Data Retention Capability,” Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 21-24, Nov. 2014.
  4. S. Izumi, K. Yamashita, M. Nakano, T. Nakagawa, Y. Kitahara, K. Yanagida, S. Yoshimoto, H. Kawaguchi, H. Kimura, K. Marumoto, T. Fuchikami, Y. Fujimori, H. Nakajima, T. Shiga, and M. Yoshimoto, “A 6.14μA Normally-Off ECG-SoC with Noise Tolerant Heart Rate Extractor for Wearable Healthcare Systems,” Proc. of IEEE BioCAS, pp. 280-283, Oct. 2014.
  5. Y. Nakai, S. Izumi, M. Nakano, K. Yamashita, T. Fujii, H. Kawaguchi, and M. Yoshimoto, “Noise Tolerant QRS Detection using Template Matching with Short-Term Autocorrelation,” 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society(EMBC), pp. 34-37, Aug. 2014.
  6. T. Nakagawa, S. Izumi, S. Yoshimoto, K. Yanagida, Y. Kitahara, H.Kawaguchi, and M. Yoshimoto, “A 6T-4C Shadow Memory using Plate Line and Word Line Boosting,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2736-2739, Jun. 2014.
  7. Y. Nakata, Y. Kimi, S. Okumura, J. Jung, T. Sawada, T. Toshikawa, M. Nagata, H. nakano, M. Yabuuchi, H. Fujiwara, K. Nii, H. Kawai, H. Kawaguchi, and M. Yoshimoto, “A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance with Bit-Enhancing Memory and On-Chip Diagnosis Structures Delivering x91 Failure Rate Improvement,” IEEE International Symposium on Quality Electronic Design (ISQED), pp. 16-23, Mar. 2014.
  8. G.Matsukawa, Y.Nakata, Y.Kimi, Y.Sugure, M.Shimozawa, S.Oho, H.Kawaguchi, and M.Yoshimoto, “A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM, ” ARCS VERFE Workshop, Feb. 2014.
  9. S. Izumi, H. Kawaguchi, M. Yoshimoto, and Y. Fujimori, “(Invited Paper) Normally-off Technologies for Healthcare Appliance,” In Proceedings of 19th IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 17-20, Jan. 2014.

2013

  1. Y. Umeki, K. Yanagida, S. Yoshimoto, S. Izumi, M. Yoshimoto, H. Kawaguchi, K. Tsunoda, T. Sugii, “A 0.38-V Operating STT-MRAM with Process Variation Tolerant Sense Amplifier,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2013.
  2. S. Izumi, M. Nakano, K. Yamashita, T. Fujii, H. Kawaguchi, and M. Yoshimoto, “Low-power Hardware Implementation of Noise Tolerant Heart Rate Extractor for a Wearable Monitoring System,” IEEE International Conference on BioInformatics and BioEngineering (BIBE), Nov. 2013.
  3. G. He, Y. Miyamoto, K. Matsuda, S. Izumi, H. Kawaguchi, M. Yoshimoto, ” A 40-nm 54-mW 3×-Real-time VLSI Processor for 60-KWORD Continuous Speech Recognition, ” Proceeding of IEEE Workshop on Signal Processing Systems (SiPS), pp.27, Oct. 2013.
  4. S. Yoshimoto, S. Miyano, M. Takamiya, H. Shinohara, H. Kawaguchi, and M. Yoshimoto, “A 40-nm 8T SRAM with Selective Source Line Control of Read Bitlines and Address Preset Structure,” IEEE Custom Integrated Circuits Conference (CICC), Sep. 2013.
  5. S. Izumi, K. Yamashita, M. Nakano, T. Konishi, H. Kawaguchi, H. Kimura, K. Marumoto, T. Fuchikami, Y. Fujimori, H. Nakajima, T. Shiga, and M. Yoshimoto, “A 14 uA ECG Processor with Robust Heart Rate Monitor for a Wearable Healthcare System,” Proceedings of IEEE European Solid-State Circuits Research Conference (ESSCIRC), pp. 145-148, Sep. 2013.
  6. S. Yoshimoto, S. Izumi, H. Kawaguchi, and M. Yoshimoto,”Soft-Error Tolerant N-P Reversed 6T SRAM Cell,” IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.
  7. T. Fujii, M. Nakano, K. Yamashita, T. Konishi, S. Izumi, H. Kawaguchi, M. Yoshimoto, “Noise Torelant Instantanous Heart Rate and R-peak Detection Using Short-term Autocorrelation for Wearable Healthcare Systems, ” Proceeding of 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), pp.7330-7333, July, 2013.
  8. K. Okuno, S. Izumi, T. Konishi, S. Dae-Woo, M. Yoshimoto, H. Kawaguchi, “Temperature Compensation Using Least Mean Squares for Fast Settling All-Digital Phase-Locked Loop, ” Proceedings of 11th IEEE New Circuits and Systems Conference (NEWCAS), June, 2013.
  9. K. Yamashita, S. Izumi, M. Nakano, T. Fujii, T. Konishi, H. Kawaguchi, H. Kimura, K. Marumoto, T. Fuchikami, Y. Fujimori, H. Nakajima, T. Shiga, M. Yoshimoto, “A 38uA Wearable Biosignal Monitoring System with Near Field Communication, ” Proceedings of 11th IEEE New Circuits and Systems Conference (NEWCAS), June, 2013.
  10. S. Yoshimoto, K. Nii, H. Kawaguchi, and M. Yoshimoto, “Multiple-Cell-Upset Hardened 6T SRAM Using NMOS-Centered Layout,” IEEE International Meeting for Future of Electron Devices Kansai (IMFEDK), pp. 98-99, June 2013.
  11. K. Takagi, K. Mizuno, S. Izumi, H. Kawaguchi, and M. Yoshimoto, “A SUB-100-MILLIWATT DUAL-CORE HOG ACCELERATOR VLSI FOR REAL-TIME MULTIPLE OBJECT DETECTION” 2013 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP2013), pp.2533-2537, May,2013.
  12. Y. Nakata, Y. Ito, Y. Takeuchi, Y. Sugure, S. Oho, H. Kawaguchi, and M. Yoshimoto, “Model-Based Fault Injection for Large-Scale Failure Effect Analysis with 600-Node Cloud Computers,” DATE RIIF Workshop, Mar. 2013.
  13. Y. Takeuchi, Y. Nakata, Y. Ito, Y. Sugure, S. Oho, H. Kawaguchi, and M. Yoshimoto, “SRAM Failure Injection to a Vehicle ECU and Its Behavior Evaluation,” DATE RIIF Workshop, Mar. 2013.
  14. J. Jung, Y. Nakata, M. Yoshimoto and H. Kawaguchi, “Energy-Efficient Spin-Transfer Torque RAM Cache Exploiting Additional All-Zero-Data Flags,” International Symposium on Quality Electornic Design (ISQED), pp. 216-222, Mar. 2013.
  15. S. Okumura, S. Yoshimoto, H. Kawaguchi and M. Yoshimoto, “A Physical Unclonable Function Chip Exploiting Load Transistors’ Variation in SRAM Bitcells,” IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) University LSI Design Contest, pp. 79-80, Jan. 2013.
  16. S. Yoshimoto, M. Terada, S. Okumura, T. Suzuki, S. Miyano, H. Kawaguchi and M. Yoshimoto, “A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Power Disturb Mitigation Technique,” IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) University LSI Design Contest, pp. 77-78, Jan. 2013.
  17. G. He, T. Sugahara, T. Fujinaga, Y. Miyamoto, H. Noguchi, S. Izumi, H. Kawaguchi and M. Yoshimoto, “A 40-nm 144-mW VLSI Processor for Realtime 60k Word Continuous Speech Recognition,” IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) University LSI Design Contest, pp. 71-72, Jan. 2013.

2012

  1. S. Soda, M. Nakamura, S. Matsumoto, S. Izumi, H. Kawaguchi, and M. Yoshimoto, “Handsfree Voice Interface for Home Network Service using a Microphone Array Network,” In Proc. of Third International Conference on Networking and Computing, pp. 195-200, Dec. 2012.
  2. K. Mizuno, Y. Terachi, K. Takagi, S. Izumi, H. Kawaguchi, and M. Yoshimoto, “Architectural Study on HOG Feature Extraction Processor for Real-Time Object Detection,” IEEE Workshop on Signal Processing Systems (SiPS), pp.197-202, Oct. 2012.
  3. G. He, T. Sugahara, Y. Miyamoto, S. Izumi, H. Kawaguchi, and M. Yoshimoto, “A 40-nm 168-mW 2.4×-Real-Time VLSI Processor for 60-kWord Continuous Speech Recognition,” IEEE Custom Integrated Circuits Conference(CICC), pp.1-4, Sep. 2012.
  4. M. Nakano, T. Konishi, S. Izumi, H. Kawaguchi, and M. Yoshimoto, “Instantaneous Heart Rate Detection Using Short-Time Autocorrelation for Wearable Healthcare Systems,” 34th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), pp.6703-6706, Aug. 2012.
  5. S. Yoshimoto, M. Terada, Y. Umeki, S. Okumura, A. Kawasumi, T. Suzuki, S. Moriwaki, S. Miyano, H. Kawaguchi and M. Yoshimoto, “A 40-nm 256-Kb Sub-10 pJ/Access 8T SRAM with ReadBitline Amplitude Limiting (RBAL) Scheme,” IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 85-90, Jul. 2012.
  6. S. Yoshimoto, T. Amashita, M. Yoshimura, Y. Matsunaga, H. Yasuura, S. Izumi, H. Kawaguchi, and M. Yoshimoto, “Neutron-Induced Soft Error Rate Estimation for SRAM Using PHITS,” IEEE International On-Line Testing Symposium (IOLTS), pp. 173-176, Jun. 2012.
  7. K. Okuno, T. Konishi, S. Izumi, M. Yoshimoto, and H. Kawaguchi, ” A 62-dB SNDR Second-Order Gated Ring Oscillator TDC with Two-Stage Dynamic D-Type Flipflops as A Quantization Noise Propagator,” IEEE International New Circuits and Systems (NEWCAS), pp.289-292, Jun. 2012.
  8. T. Konishi, K. Okuno, S. Izumi, M. Yoshimoto, and H. Kawaguchi, ” A 61- dB SNDR 700 um2 Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops,” Symposium on VLSI Circuits, pp. 190-191, June 2012.
  9. J. Jung, Y. Nakata, S. Okumura, H. Kawaguchi, and M. Yoshimoto, “A Variation-Aware 0.57-V Set-Associative Cache with Mixed Associativity Using 7T/14T SRAM,” IEEE Faible Tension Faible Consommation (FTFC), Jun. 2012.
  10. Y. Nakata, S. Izumi, H. Kawaguchi, and M. Yoshimoto, “Trading off ECU Footprint for Reliability in X-by-Wire Application with Hybrid TMR Architecture,” DAC International Workshop on System Level-Design of Automotive Electronics/Software (SLDAES), Jun. 2012.
  11. T. Konishi, K. Okuno, S. Izumi, M. Yoshimoto, and H. Kawaguchi, ” A 51- dB SNDR DCO-Based TDC Using Two-Stage Second-Order Noise Shaping,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3170-3173, Seoul, Korea, May 2012.
  12. S. Yoshimoto, T. Amashita, S. Okumura, K. Nii, H. Kawaguchi, and M. Yoshimoto, “NMOS-Inside 6T SRAM Layout Reducing Neutron-Induced Multiple Cell Upsets,” IEEE International Reliability Physics Symposium (IRPS), pp. 5B.5.1-5, Apr. 2012.
  13. M. Terada, S. Yoshimoto, S. Okumura, T. Suzuki, S. Miyano, H. Kawaguchi, and M. Yoshimoto, “A 40-nm 256-Kb 0.6-V Operation Half-Select Resilient 8T SRAM with Sequential Writing Technique Enabling 367-mV VDDmin Reduction,” Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), Mar. 2012.
  14. Y. Kagiyama, S. Okumura, K. Yanagida, S. Yoshimoto, Y. Nakata, S. Izumi, H. Kawaguchi, and M. Yoshimoto, “Bit Error Rate Estimation in SRAM Considering Temperature Fluctuation,” Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), Mar. 2012.
  15. K. Kugata, S. Soda, Y. Nakata, S. Okumura, S. Izumi, M. Yoshimoto, and H. Kawaguchi, “Processor Coupling Architecture for Aggressive Voltage Scaling on Multicores,” ARCS Workshops 2012, pp. 375-384, Mar. 2012.

2011

  1. M. Nishino, H. Noguchi, Y. Shimai, S. Izumi, H. Kawaguchi and M. Yoshimoto, “A75-Variable MIQP Solver Processor for Real-Time Autonomous RobotControl,” Proceedings of 2011 IEEE/SICE International Symposiumon System Integration (SII), Dec. 2011.
  2. J. Jung, Y. Nakata, S. Okumura, H. Kawaguchi, and M. Yoshimoto, “256-KB Associativity-Reconfigurable Cache with 7T/14T SRAM for Aggressive DVS Down to 0.57 V ,” Proceedings of 18th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 524-527, Dec. 2011.
  3. G. He, T. Sugahara, T. Fujinaga, Y. Miyamoto, H. Noguchi, S. Izumi, H. Kawaguchi, M. Yoshimoto, “A 40 nm 144 mW VLSI Processor for Realtime 60 kWord Continuous Speech Recognition,” Proceedings of IEEE Custom Integrated Circuits Conference (CICC), Sep. 2011.
  4. S. Okumura, Y. Nakata, K. Yanagida, Y. Kagiyama, S. Yoshimoto, H. Kawaguchi, and M. Yoshimoto, “Low-Power Block-Level Instantaneous Comparison 7T SRAM for Dual Modular Redundancy,” Proceedings of IEEE Custom Integrated Circuits Conference (CICC), Sep. 2011.
  5. S. Okumura, S. Yoshimoto, H. Kawaguchi and M. Yoshimoto, ” A 128-bit Chip Identification Generating Scheme Exploiting SRAM Bitcells with Failure Rate of 4.45 × 10-19,” Proceedings of IEEE European Solid-State Circuits Research Conference (ESSCIRC), Sep. 2011.
  6. Y. Nakata, Y. Takeuchi, H. Kawaguchi and M. Yoshimoto, “A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Router,” 14th Euromicro Conference on Digital System Design (DSD), Aug. 2011.
  7. S. Izumi, H. Noguchi, T. Takagi, K. Kugata, S. Soda, M. Yoshimoto, and H. Kawaguchi, “Data Aggregation Protocol for Multiple Sound Sources Acquisition with Microphone Array Network,” Proceedings of 20th International Conference on Computer Communications and Networks (ICCCN), Jul. 2011.
  8. S. Yoshimoto, T. Amashita, D. Kozuwa, T. Takata, M. Yoshimura, Y. Matsunaga, H. Yasuura, H. Kawaguchi and M. Yoshimoto, “Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure,” IEEE International On-Line Testing Symposium (IOLTS), pp.151-156, Jul. 2011.
  9. Y. Nakata, Y. Ito, Y. Sugure, S. Oho, Y. Takeuchi, S. Okumura, H. Kawaguchi and M. Yoshimoto, “Model-Based Fault Injection for Failure Effect Analysis -Evaluation of Dependable SRAM for Vehicle Control Units-,” 5th Workshop on Dependable and Secure Nanocomputing (WDSN), in conjunction with the 41st International Conference on Dependable Systems and Networks (DSN) , Jun. 2011.
  10. S. Yoshimoto, M. Terada, S. Okumura, T. Suzuki, S. Miyano, H. Kawaguchi and M. Yoshimoto, “A 40-nm 0.5-V 20.1-uW/MHz 8T SRAM with Low-Energy Disturb Mitigation Scheme,” Digest of Technical Papers 2011 Symposium on VLSI Circuits, Jun. 2011.
  11. Shimpei Soda, Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi ,”Positioning System for Mobile Terminals Using a Microphone Array Network as an Intuitive Interface”, The Third Joint Workshop on Hands-free Speech Communication and Microphone Arrays(HSCMA), May. 2011.
  12. T. Konishi, H. Lee, S. Izumi, M. Yoshimoto, and H. Kawaguchi, ” A 40-nm 640-μm2 45-dB Opampless All-Digital Second-Order MASH ΔΣ ADC,” Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 518-521, Rio de Janeiro, Brazil, May 2011.
  13. S. Yoshimoto, T. Amashita, S. Okumura, K. Yamaguchi, M. Yoshimoto and H. Kawaguchi, “Bit Error and Soft Error Hardenable 7T/14T SRAM with 150-nm FD-SOI Process,” IEEE International Reliability Phisics Symposium (IRPS), pp. 876-881, Apr. 2011.
  14. S. Yoshimoto, T. Amashita, D. Kozuwa, T. Takata, M. Yoshimura, Y. Matsunaga, H. Yasuura, H. Kawaguchi, and M. Yoshimoto, “Multiple-Bit- Upset Tolerant 8T SRAM Cell Layout with Divided Wordline Structure,” Proceedings of Silicon Errors in Logic – System Effects (SELSE), pp. 106 -111, Mar. 2011.
  15. M. Yoshikawa, S. Okumura, Y. Nakata, Y. Kagiyama, H. Kawaguchi and M. Yoshimoto, “Block-Basis On-Line BIST Architecture for Embedded SRAM Using Wordline and Bitcell Voltage Optimal Control,” Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 322- 325 Mar. 2011.
  16. H. Noguchi, S. Okumura, T. Takagi, K. Kugata, M. Yoshimoto and H. Kawaguchi,“0.45-V Operating Vt-Variation Tolerant 9T/18T Dual-Port SRAM, Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 219-222 Mar. 2011.
  17. K. Yamaguchi, S. Okumura, M. Yoshimoto and H. Kawaguchi, “0.42-V 576-kb 0.15-um FD-SOI SRAM with 7T/14T Bit Cells and Substrate Bias Control Circuits for Intra-Die and Inter-Die Variability Compensation,” Proceedings of 7th Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EUROSOI), pp. 37-38, Granada, SPAIN, Jan. 17-19, 2011.

2010

  1. S. Yoshimoto, S. Okumura, H. Kawaguchi, and M. Yoshimoto, “The Area Criteria of 6T and 8T SRAM Cells,” IEEE/ACM Workshop on Variability Modeling and Characterization (VMC), p.4, Nov. 2010.
  2. S. Izumi, T. Takeuchi, T. Matsuda, H. Lee, T. Konishi, K. Tsuruda, Y. Sakai, C. Ohta, H. Kawaguchi, and M. Yoshimoto, “A 58-uW Sensor Node LSI with Synchronous MAC Protocol,” Proceedings of Asia-aPacific Radio Science Conference (AP-RASC), Toyama, Japan, Sep. 2010.
  3. S. Okumura, S. Yoshimoto, K. Yamaguchi, Y. Nakata, H. Kawaguchi, and M. Yoshimoto, “7T SRAM Enabling Low-Energy Simultaneous Block Copy,” Proceedings of IEEE Custom Integrated Circuits Conference (CICC), Dig. Tech. Papers, Sep. 2010.
  4. H. Noguchi, J. Tani, Y. Shimai, M. Nishino, S. Izumi, H. Kawaguchi, and M. Yoshimoto, “A 34.7-mW Quad-Core MIQP Solver Processor for Robot Control,” Proceedings of IEEE Custom Integrated Circuits Conference (CICC), Sep. 2010.
  5. K. Mizuno, H. Noguchi, G. He, Y. Terachi, T. Kamino, H. Kawaguchi and M. Yoshimoto, “Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video,” Proceedings of 20th International Conference on Field Programmable Logic and Applications (FPL), pp608-611, Milano, ITALY, Aug. 2010.
  6. Y. Nakata, S. Okumura, H. Kawaguchi, and M. Yoshimoto, “0.5-V Operation Variation-Aware Word-Enhancing Cache Architecture Using 7T/14T hybrid SRAM,” Proceedings of International Symposium on Low Power Electronics and Design (ISLPED), pp. 219-224, Aug. 2010.
  7. Y. Takeuchi, Y. Nakata, H. Kawaguchi, and M. Yoshimoto, “Scalable Parallel Processing for H.264 Encoding Application to Multi/Many-core Processor,” Proceedings of the International Conference on Intelligent Control and Information Processing (ICICIP), pp. 163-170, Aug. 2010.
  8. S. Izumi, K. Tsuruda, T. Takeuchi, H. Lee, H. Kawaguchi, and M. Yoshimoto, “A Low-Power Multi Resolution Spectrum Sensing (MRSS) Architecture for a Wireless Sensor Network with Cognitive Radio,” Proceedings of International Conference on Sensor Technologies and Applications (SENSORCOMM 2010), pp. 39-44, Jul. 2010.
  9. H. Noguchi, T. Takagi, K. Kugata, M. Yoshimoto, and H. Kawaguchi, “A Low-Traffic and Low-Power Data-Intensive Sound Acquisition System with Perfect Aggregation Scheme Specialized for Microphone Array Network,” Proceedings of International Conference on Sensor Technologies and Applications (SENSORCOMM 2010), pp. 157-162, July 2010.
  10. K. Kugata, T. Takagi, H. Noguchi, M. Yoshimoto, and H. Kawaguchi, “Live demonstration: Intelligent ubiquitous sensor network for sound acquisition,” Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), p. 1413, May 2010.
  11. K. Kugata, T. Takagi, H. Noguchi, M. Yoshimoto, and H. Kawaguchi, “Intelligent ubiquitous sensor network for sound acquisition,” Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1414-1417, May 2010.
  12. H. Noguchi, J. Tani, Y. Shimai, H. Kawaguchi, and M. Yoshimoto, ” Parallel-Processing VLSI Architecture for Mixed Integer Linear Programming,” Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2362-2365, May 2010.
  13. T. Takagi, H. Noguchi, K. Kugata, M. Yoshimoto, and H. Kawaguchi, “Microphone Array Network for Ubiquitous Sound Acquisition,” Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp. 1474-1477, Mar. 2010.

2009

  1. Y. Shimai, J. Tani, H. Noguchi, H. Kawaguchi, and M. Yoshimoto, “FPGA Implementation of Mixed Integer Quadratic Programming Solver for Mobile Robot Control,” Proceedings of IEEE International Conference on Field-Programmable Technology (FPT), pp. 447-450, Dec. 2009.
  2. T. Takeuchi, S. Izumi, T. Matsuda, H. Lee, T. Konishi, K. Tsuruda, Y. Sakai, H. Kawaguchi and M. Yoshimoto, “A Single-Chip Sensor Node LSI with Synchronous MAC Protocol and Divided Data-Buffer SRAM,” Proceedings of International SoC Design Conference 2009 , Nov. 2009.
  3. H. Noguchi, T. Takagi, M. Yoshimoto, and H. Kawaguchi, “An Ultra-Low-Power VAD Hardware Implementation for Intelligent Ubiquitous Sensor Networks,” Proceedings of IEEE Workshop on Signal Processing Systems (SiPS), pp. 214-219, Oct. 2009.
  4. T. Fujinaga, K. Miura, H. Noguchi, H. Kawaguchi, and M. Yoshimoto, “Parallelized Viterbi Processor for 5,000-Word Large-Vocabulary Real-Time Continuous Speech Recognition FPGA System,” Proceedings of ISCA Annual Conference of International Speech Communication Association (Interspeech), pp.1483-1486, Sep. 2009.
  5. T. Konishi, K. Tsuruda, S. Izumi, H. Lee, H. Fujiwara,T. Takeuchi, H. Kawaguchi, and M. Yoshimoto, “A 60-dB Image Rejection Filter Using Δ-Σ Modulation and Frequency Shifting,” 2009 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Victoria, B.C., Canada, pp. 565-570, Aug. 2009.
  6. T. Takeuchi, S. Izumi, T. Matsuda, H. Lee, Y. Otake, T. Konishi, K. Tsuruda, Y. Sakai, H. Fujiwara, C. Ohta, H. Kawaguchi and M. Yoshimoto, “58-uW Single-Chip Sensor Node Processor Using Synchronous MAC Protocol, ” Digest of Technical Papers 2009 Symposium on VLSI Circuits, pp. 290- 291, June. 2009.
  7. S. Okumura, Y. Iguchi, S. Yoshimoto, H. Fujiwara, H. Noguchi, K. Nii, H. Kawaguchi, and M. Yoshimoto, “A 0.56-V 128kb 10T SRAM Using Column Line Assist (CLA) Scheme,” Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), pp. 659-663, Mar. 2009.
  8. H. Fujiwara, S. Okumura, Y. Iguchi, H. Noguchi, H. Kawaguchi, and M. Yoshimoto, “A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection,” Proceedings of IEEE International Conference on VLSI Design, pp. 295-300, Jan. 2009.

2008

  1. K. Tsuruda, S. Izumi, H. Lee, T. Takeuchi, H. Kawaguchi, and M. Yoshimoto, “A Flexible Baseband Processor with Multi-Resolution Spectrum-Sensing Functionality,” International Symposium on Information Theory and its Applications, Auckland, New Zealand, pp. 1423-1428, Dec, 2008.
  2. K. Miura, H. Noguchi, H. Kawaguchi, and M. Yoshimoto, “A Low Memory Bandwidth Gaussian Mixture Model (GMM) Processor for 20,000-Word Real-Time Speech Recognition FPGA System,” Proceedings of IEEE International Conference on Field-Programmable Technology (FPT), pp. 341-344, Dec. 2008.
  3. H. Fujiwara, T. Takeuchi, Y. Otake, M. Yoshimoto, and H. Kawaguchi, “An Inter-Die Variability Compensation Scheme for 0.42-V 486-kb FD-SOI SRAM using Substrate Control,” 2008 IEEE International SOI Conference, New Paltz, New York, USA, Oct. 2008.
  4. K. Mizuno, J. Miyakoshi, Y. Murachi, M. Hamamoto, T. Iinuma, T. Ishihara, F. Yin, J. Lee, T. Kamino, H. Kawaguchi, and M. Yoshimoto. “An H.264/AVC MP@L4.1 Quarter-Pel Motion Estimation Processor VLSI for Real-Time MBAFF Encoding”IEEE International Conference on Electronics, Circuits, and Systems(ICECS 2008), St.Julians, Malta, Sep 2008.
  5. H. Noguchi, S. Okumura, Y. Iguchi, H. Fujiwara, Y. Morita, K. Nii, H. Kawaguchi, and M. Yoshimoto, “Which is the Best Dual-Port SRAM in 45-nm Process Technology? – 8T, 10T Single End, and 10T Differential -,” Proceedings of IEEE International Conference on IC Design and Technology (ICICDT), pp.55-58, June 2008.
  6. Y. Murachi, K. Mizuno, J. Miyakoshi, M. Hamamoto, T. Iinuma, T. Ishihara, F. Yin, J. Lee, T. Kamino, H. Kawaguchi, and M. Yoshimoto. “A Sub 100 mW H.264/AVC MP@L4.1 Integer-Pel Motion Estimation Processor VLSI for MBAFF Encoding”International Symposium on Circuits and Systems(ISCAS),Seattle, Washington, USA, May 2008.
  7. Y. Murachi, T. Kamino, J. Miyakoshi, H. Kawaguchi and M. Yoshimoto, “A Power-Efficient SRAM Core Architecture with Segmentation-Free and Rectangular Accessibility for Super-Parallel Video Processing,” 2008 International Symposium on VLSI Design, Automation & Test (VLSI-DAT), Hsinchu, Taiwan, pp. 63-66, April 2008.
  8. S. Izumi, T. Matsuda, H. Kawaguchi, C. Ohta, and M. Yoshimoto, “Hop Count Aware Broadcast Algorithm with Random Assessment Delay Extension for Wireless Sensor Networks,” Asia-Pacific Symposium on Information and Telecommunication Technologies (APSITT), pp. 30-35, Apr. 2008.
  9. T. Matsuda, S. Izumi, T. Takeuchi, H. Fujiwara, H. Kawaguchi, C. Ohta, and M. Yoshimoto, “Impact of Random Access Memory aware Data Aggregation for Wireless Sensor Network,” Asia-Pacific Symposium on Information and Telecommunication Technologies (APSITT), pp. 130-134, Apr. 2008.
  10. H. Fujiwara, S. Okumura, Y. Iguchi, H. Noguchi, Y. Morita, H. Kawaguchi, and M. Yoshimoto, “Quality of a Bit (QoB): A New Concept in Dependable SRAM,” 9th International Symposium on Quality Electronic Design (ISQED 2008), San Jose, California, pp. 98-102, USA, March 2008.
  11. T. Ishihara, Y. Murachi, T. Iinuma, F. Yin, T. Kamino, K. Mizuno, H. Kawaguchi, and M. Yoshimoto, International Solid-State Circuits Conference student forum, San Francisco, California, USA, Feb. 2008.

2007

  1. T. Matsuda, T. Aonishi, T. Takeuchi, H. Kawaguchi, C. Ohta, and M. Yoshimoto, “Multipath Routing using Isochronous Medium Access Control with Multi Wakeup Period for Wireless Sensor Networks,” Proc. 4th IEEE International Symposium on Wireless Communication Systems 2007 (ISWCS 2007), pp.718-721, Trondheim, Norway, Oct. 2007.
  2. Y. Otake, M. Ichien, T. Takeuchi, A. Gion, S. Mikami, H. Fujiwara, H. Kawaguchi, C. Ohta, and M. Yoshimoto, “Cross-Layer Design for Low-Power Wireless Sensor Node using Long-Wave Standard Time Code,” Proc. International Conference on Sensor Technologies and Applications (SENSORCOMM 2007), pp.341-346, Valencia, Spain, Oct. 2007.
  3. S. Izumi, T. Matsuda, H. Kawaguchi, C. Ohta, and M. Yoshimoto, “Improvement of Counter-based Broadcasting by Random Assessment Delay Extension for Wireless Sensor Networks,” Proc. International Conference on Sensor Technologies and Applications (SENSORCOMM 2007), pp.76-81, Valencia, Spain, Oct. 2007.
  4. Y. Sakata, K. Kawakami, H. Kawaguchi, and M. Yoshimoto, “An elastic pipeline architecture for dynamic voltage scaling and its application to low-power portable H.264/AVC decoder with embedded frame buffer SRAM,” EUROPEAN COMPUTING CONFERENCE, Athens, Greece, Sept. 2007.
  5. Y. Morita, H. Fujiwara, H. Noguchi, Y. Iguchi, K. Nii, H. Kawaguchi, and M. Yoshimoto, “An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment,” 2007 Symposium on VLSI Circuits Digest of Technical Papers, pp.256-257, Kyoto, Japan, June 2007.
  6. H. Noguchi, Y. Iguchi, H. Fujiwara, Y. Morita, K. Nii, H. Kawaguchi, and M. Yoshimoto, “A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing,” Proc. IEEE Computer Society Annual Symposium on VLSI 2007 (ISVLSI 2007), pp.107-112, Porto Alegre, Brazil, May 2007.
  7. Y. Higuchi, A. Foronda, C. Ohta, M. Yoshimoto, and Y. Okada, “Delay Guarantee and Service Interval Optimization for HCCA in IEEE 802.11e WLANs,” Proc. IEEE Wireless Communications and Networking Conference (WCNC 2007), Hong Kong, China, March 2007.
  8. K. Kawakami, M. Kuroda, H. Kawaguchi, M. Yoshimoto, “Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture,” Proc. 12th Asia and South Pacific Design Automation Conference (12th ASP-DAC), pp.292-297, Yokohama, Japan, Jan. 2007.
  9. S. Mikami, T. Takeuchi, H. Kawaguchi, C. Ohta, and M. Yoshimoto, “An Efficiency Degradation Model of Power Amplifier and the Impact against Transmission Power Control,” Proc. IEEE 2007 Radio and Wireless Symposium (RWS 2007), pp.447-450, Long Beach, California, USA, Jan. 2007.
  10. S. Mikami, M. Ichien, T. Takeuchi, H. Kawaguchi, C. Ohta, and M. Yoshimoto, “A 356-µW, 433-MHz, Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks,” Proc. IEEE 2007 Radio and Wireless Symposium (RWS 2007), pp.451-454, Long Beach, California, USA, Jan. 2007.

2006

  1. T. Iinuma, J. Miyakoshi, Y. Murachi, T. Matsuno, M. Hamamoto, T. Ishihara, H. Kawaguchi, M. Miyama, and M. Yoshimoto, “An 800-µW H.264 Baseline-Profile Motion Estimation Processor Core,” 2006 IEEE Asian Solid-State Circuits Conference Proceedings, pp.99-102, Hangzhou, China, Nov. 2006.
  2. J. Miyakoshi, Y. Murachi, T. Matsuno, M. Hamamoto, T. Iinuma, T. Ishihara, H. Kawaguchi, and M. Yoshimoto, “A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing,” Proc. 14th IFIP International Conference on Very Large Scale Integration (VLSI-SoC 2006), pp.192-197, Nice, France, Oct. 2006.
  3. M. Ichien, T. Takeuchi, S. Mikami, H. Kawaguchi, C. Ohta, and M. Yoshimoto, “Isochronous MAC using Low Frequency Radio Wave Time Synchronization for Wireless Sensor Networks,” Proc. First International Conference on Communications and Electronics (ICCE 2006), pp.172-177, Hanoi, Vietnam, Oct. 2006.
  4. T. Matsuda, T. Takeuchi, H. Yoshino, M. Ichien, S. Mikami, H. Kawaguchi, C. Ohta, and M. Yoshimoto, “A Power-Variation Model for Sensor Node and the Impact against Life Time of Wireless Sensor Networks,” Proc. First International Conference on Communications and Electronics (ICCE 2006), pp.106-111, Hanoi, Vietnam, Oct. 2006.
  5. T. Matsuda, M. Ichien, S. Mikami, H. Kawaguchi, C. Ohta, and M. Yoshimoto, “Data Transmission Scheduling based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks,” First International Conference on Communications and Electronics (ICCE 2006), Hanoi, Vietnam, Oct. 2006.
  6. H. Fujiwara, K. Nii, J. Miyakoshi, Y. Murachi, Y. Morita, H. Kawaguchi, and M. Yoshimoto, “A Two-Port SRAM for Real-Time Video Processor Saving 53% of Bitline Power with Majority Logic and Data-Bit Reordering,” Proc. International Symposium on Low Power Electronics and Design (ISLPED), pp.61-66, Tegernsee, Germany, Oct. 2006.
  7. T. Aonishi, T. Matsuda, S. Mikami, C. Ohta, H. Kawaguchi, and M. Yoshimoto, “Impact of Aggregation Efficiency on GIT Routing for Wireless Sensor Networks,” Proc. International Workshop on Wireless and Sensor Networks, Columbus, Ohio, USA, Aug. 2006.
  8. Y. Morita, H. Fujiwara, H. Noguchi, K. Kawakami, J Miyakoshi, S. Mikami, K. Nii, H. Kawaguchi, and M. Yoshimoto, “A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC under DVS Environment,” 2006 Symposium on VLSI Circuits Digest of Technical Papers, pp.16-17, Honolulu, Hawaii, USA, June 2006.
  9. R. Yamamoto, Y. Fukuyama, T. Katagiri, J. Miyakoshi, Y. Kuroda, N. Minegishi, M. Miyama, H. Kawaguchi, K. Imamura, H. Hashimoto, and M. Yoshimoto, “An Architecture Study of Scalable Optical-Flow Processor for Real-Time Video Segmentation,” Proc. IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips IX), pp. 225-240, Yokohama, Japan, April 2006.

2005

  1. S. Mikami, T. Matsuno, M. Miyama, M. Yoshimoto, and H. Ono, “A Wireless-Interface SoC Powered by Energy Harvesting for Short-range Data Communication,” 2005 IEEE Asian Solid-State Circuits Conference Proceedings, pp.241-244, Hsinchu, Taiwan, Nov. 2005.
  2. Y. Murachi, K. Hamano, T. Matsuno, J. Miyakoshi, M. Miyama, and M. Yoshimoto, “A 95mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High Resolution Video Application”, 2005 Symposium on VLSI Circuits Dig. Tech. Papers, pp.212-215, Kyoto, Japan, June 2005.

2004

  1. J. Miyakochi, Y. Kuroda, M. Miyama, K. Imamura, H. Hashimoto and M. Yoshimoto, “A 400µW MPEG-4 Motion Estimation Processor Core for Mobile Video Application,” Proc. IP-Based SoC Design Forum and Exhibition (IP/SoC 2004), Grenoble, France, Dec. 2004.
  2. M. Yoshimoto, and K. Kawakami, “A Feed-Foreward Dynamic Voltage Frequency Management by Workload Prediction for a Low Power Motion Video Compression,” Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 365-370, Kanazawa, Japan, Oct. 2004.
  3. K. Kawakami, M. Kanamori, Y. Morita, J. Takemura, J. Miyakoshi, H. Ohira, M. Miyama, and M. Yoshimoto, “A Feed-Forward Dynamic Voltage Frequency Management for Power-Minimum Motion Video Compression in Sub-Decimicron Era,” Sixth Biannual World Automation Congress (WAC 2004) Proceedings, Vol.18, pp.279-284, Seville, Spain, June 2004.
  4. Y. Kuroda, J. Miyakoshi, M. Miyama, K. Imamura, H. Hashimoto, and M. Yoshimoto, “A sub-mW MPEG-4 motion estimation processor core for mobile video application,” Proc. Asia and South Pasific Design Automation Conference 2004, pp.527-528, Yokohama, Japan, Jan. 2004.

2003

  1. J. Miyakoshi, Y. Kuroda, M. Miyama, K. Imamura, H. Hashimoto and M. Yoshimoto, “A Sub-mW MPEG-4 Motion Estimation Processor Core for Mobile Video Application,” Proc. IEEE 2003 Custom Integrated Circuit Conference (CICC), pp.181-184, San Jose, California, USA, Sept. 2003.
  2. K. Kawakami, H. Ohira, M. Kanamori, M. Miyama and M. Yoshimoto, “A Feed-Forward Dynamic Voltage Control Algorithm for Low Power/High Quality MPEG4 on Multi-regulated Voltage CPU,” Proc. IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips VI), Vol. 1, pp. 87-101, Yokohama, Japan, April 2003.

2002

  1. M. Miyama, O. Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, J. Miyakoshi, H. Hashimoto, S. Komatsu, M. Yagi, K. Taki, and M. Yoshimoto, “An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm,” Proc. IEEE 2002 Custom Integrated Circuit Conference (CICC), pp.167-170, Orlando, Florida, USA, May 2002.