Dissertation

  1. H. Kawaguchi, "A Study on Low-Power Circuit Design for Silicon VLSI's and Organic IC's in Ubiquitous Electronics Environment," The University of Tokyo, Jan. 19. 2006.

    Transactions/Journals

  2. H. Kawaguchi, and T. Sakurai, "A Reduced Clock-Swing Flip-Flop (RCSFF) for 63% Power Reduction," IEEE Journal of Solid-State Circuits, vol. 33, no. 5, pp. 807-811, May 1998.
  3. H. Kawaguchi, K. Nose, and T. Sakurai, "A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Picoampere Stand-By Current," IEEE Journal of Solid-State Circuits, vol. 35, no. 10, pp. 1498-1501, Oct. 2000.
  4. T. Hiramoto, M. Takamiya, H. Koura, T. Inukai, H. Gomyo, H. Kawaguchi, and T. Sakurai, "Optimum Device Parameters and Scalability of Variable Threshold Voltage Complementary MOS (VTCMOS)," Japanese Journal of Applied Physics, vol. 40, part 1, no. 4B, pp. 2854-2858, Apr. 2001.
  5. K. Kanda, K. Nose, H. Kawaguchi, and T. Sakurai, "Design Impact of Positive Temperature Dependence on Drain Current in Sub-1-V CMOS VLSIs," IEEE Journal of Solid-State Circuits, vol. 36, no. 10, pp. 1559-1564, Oct. 2001.
  6. H. Kawaguchi, G. Zhang, S. Lee, Y. Shin, and T. Sakurai, "A Controller LSI for Realizing VDD-Hopping Scheme with Off-the-Shelf Processors and Its Application to MPEG4 System," IEICE Transactions on Electronics, vol. E85-C, no. 2, pp. 263-271, Feb. 2002.
  7. K. Nose, M. Hirabayashi, H. Kawaguchi, S. Lee, and T. Sakurai, "VTH-Hopping Scheme to Reduce Subthreshold Leakage for Low-Power Processors," IEEE Journal of Solid-State Circuits, vol. 37, no. 3, pp. 413-419, Mar. 2002.
  8. Y. Kato, S. Iba, R. Teramoto, T. Sekitani, T. Someya, H. Kawaguchi, and T. Sakurai, "High mobility of pentacene field-effect transistors with polyimide gate dielectric layers," Applied Physics Letters, vol. 84, no. 19, pp. 3789-3791, May 2004.
  9. T. Someya, T. Sekitani, S. Iba, Y. Kato, H. Kawaguchi, and T. Sakurai, "A large-area, flexible pressure sensor matrix with organic field-effect transistors for artificial skin applications," Proceedings of the National Academy of Sciences of the United States of America, vol. 101, no. 27, pp. 9966-9970, July 2004.
  10. H. Kawaguchi, T. Someya, T. Sekitani, and T. Sakurai, "Cut-and-Paste Customization of Organic FET Integrated Circuit and Its Application to Electronic Artificial Skin," IEEE Journal of Solid-State Circuits, vol. 40, no. 1, pp. 177-185, Jan. 2005.
  11. H. Kawaguchi, Y. Shin, and T. Sakurai, "µITRON-LP: Power-Conscious Real-Time OS Based on Cooperative Voltage Scaling for Multimedia Applications," IEEE Transactions on Multimedia, vol. 7, no. 1, pp. 67-74, Feb. 2005.
  12. K. Min, K. Kanda, H. Kawaguchi, K. Inagaki, F. R. Saliba, H. Choi, H. Choi, D. Kim, D. Kim, M. Min, and T. Sakurai, "Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's," IEICE Transactions on Electronics, vol. E88-C, no. 4, pp. 760-767, Apr. 2005.
  13. K. Toyama, S. Misaka, K. Aisaka, T. Aritsuka, K. Uchiyama, K. Ishibashi, H. Kawaguchi, and T. Sakurai, "Frequency-Voltage Cooperative CPU Power Control: A Design Rule and Its Application by Feedback Prediction," Systems and Computers in Japan, vol. 36, no. 6, pp. 39-48, June 2005.
  14. S. Iba, T. Sekitani, Y. Kato, T. Someya, H. Kawaguchi, M. Takamiya, T. Sakurai, and S. Takagi, "Control of threshold voltage of organic field-effect transistors with double-gate structures," Applied Physics Letters, vol. 87, no. 023509, July 2005.
  15. T. Someya, Y. Kato, T. Sekitani, S. Iba, Y. Noguchi, Y. Murase, H. Kawaguchi, and T. Sakurai, "Conformable, flex, large-area networks of pressure and thermal sensors with organic transistor active matrixes," Proceedings of the National Academy of Sciences of the United States of America, vol. 102, no. 35, pp. 12321-12325, Aug. 2005.
  16. T. Someya, Y. Kato, S. Iba, Y. Noguchi, T. Sekitani, H. Kawaguchi, and T. Sakurai, "Integration of Organic FETs With Organic Photodiodes for a Large Area, Flexible, and Lightweight Sheet Image Scanners," IEEE Transactions on Electron Devices, vol. 52, no. 11, pp. 2502-2511, Nov. 2005.
  17. S. Iba, Y. Kato, T. Sekitani, H. Kawaguchi, T. Sakurai, and T. Someya, "Use of laser drilling in the manufacture of organic inverter circuits," Analytical and Bioanalytical Chemistry, vol. 384, no. 2, pp. 374-377, Jan. 2006.
  18. T. Someya, T. Sekitani, S. Iba, Y. Kato, T. Sakurai, and H. Kawaguchi, "Organic Transistor Integrated Circuits for Large-Area Sensors," Molecular Crystals and Liquid Crystals, vol. 444, pp. 13-22, Jan. 2006.
  19. C. Q. Tran, H. Kawaguchi, and T. Sakurai, "Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping," IEICE Transactions on Electronics, vol. E89-C, no. 3, pp. 280-286, Mar. 2006.
  20. D. D. Antono, K. Inagaki, H. Kawaguchi, and T. Sakurai, "Trends of On-Chip Interconnects in Deep Sub-Micron VLSI," IEICE Transactions on Electronics, vol. E89-C, no. 3, pp. 392-394, Mar. 2006.
  21. K. Ishida, K. Kanda, A. Tamtrakarn, H. Kawaguchi, and T. Sakurai, "Managing Subthreshold Leakage in Charge-Based Analog Circuits with Low-VTH Transistors by Analog T-Switch (AT-Switch) and Super Cut-off CMOS (SCCMOS)," IEEE Journal of Solid-State Circuits, vol. 41, no. 4, pp. 859-867, Apr. 2006.
  22. K. Min, H. Choi, H. Choi, H. Kawaguchi, and T. Sakurai, "Leakage-Suppressed Clock-Gating Circuit with Zigzag Super Cut-Off CMOS (ZSCCMOS) for Leakage-Dominant Sub-70-nm and sub-1-V-VDD LSIs," IEEE Transactions on Very Large Scale Integration Systems, vol. 14, no. 4, pp. 430-435, Apr. 2006.
  23. S. Mikami, T. Matsuno, M. Miyama, H. Kawaguchi, M. Yoshimoto, and H. Ono, "An Energy-Harvesting Wireless-Interface SoC for Short-Range Data Communication," IEEJ Transactions on Electronics, Information and Systems, vol. 126, no. 5, pp. 565-570, May 2006.
  24. H. Kawaguchi, S. Iba, Y. Kato, T. Sekitani, T. Someya, and T. Sakurai, "A 3D-Stack Organic Sheet-Type Scanner with Double-Wordline and Double-Bitline Structure," IEEE Sensors Journal, vol. 6, no. 5, pp. 1209-1217, Oct. 2006.
  25. S. Mikami, T. Aonishi, H. Yoshino, C. Ohta, H. Kawaguchi, and M. Yoshimoto, "Aggregation Efficient-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks," IEICE Transactions on Communications, vol. E89-B, no. 10, pp. 2741-2751, Oct. 2006.
  26. K. Onizuka, H. Kawaguchi, M. Takamiya, and T. Sakurai, "VDD-Hopping Accelerators for On-Chip Power Supply Circuit to Achieve Nano-Second Order Transient Time," IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2382-2389, Nov. 2006.
  27. J. Miyakoshi, Y. Murachi, T. Ishihara, H. Kawaguchi, and M. Yoshimoto, "A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing," IEICE Transactions on Electronics, vol. E89-C, no. 11, pp. 1629-1636, Nov. 2006.
  28. D. D. Antono, K. Inagaki, H. Kawaguchi, and T. Sakurai, "Simple Waveform Model of Inductive Interconnects by Delayed Quadratic Transfer Function with Application to Scaling Trend of Inductive Effects in VLSI's," IEICE Transactions on Fundamentals, vol. E89-A, no. 12, pp. 3569-3578, Dec. 2006.
  29. J. Miyakoshi, Y. Murachi, T. Matsuno, M. Hamamoto, T. Iinuma, T. Ishihara, H. Kawaguchi, M. Miyama, and M. Yoshimoto, "A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture," IEICE Transactions on Fundamentals, vol. E89-A, no. 12, pp. 3623-3633, Dec. 2006.
  30. Y. Morita, H. Fujiwara, H. Noguchi, K. Kawakami, J. Miyakoshi, S. Mikami, K. Nii, H. Kawaguchi, and M. Yoshimoto, "A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond," IEICE Transactions on Fundamentals, vol. E89-A, no. 12, pp. 3634-3641, Dec. 2006.
  31. K. Kawakami, J. Takemura, M. Kuroda, H. Kawaguchi, and M. Yoshimoto, "A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline," IEICE Transactions on Fundamentals, vol. E89-A, no. 12, pp. 3642-3651, Dec. 2006.
  32. M. Takamiya, T. Sekitani, Y. Kato, H. Kawaguchi, T. Someya, and T. Sakurai, "An Organic FET SRAM With Back Gate to Increase Static Noise Margin and Its Application to Braille Sheet Display," IEEE Journal of Solid-State Circuits, vol. 42, no. 1, pp. 93-100, Jan. 2007.
  33. F. R. Saliba, H. Kawaguchi, and T. Sakurai, "A Self-Alignment Row-by-Row Variable-VDD Scheme Reducing 90% of Active-Leakage Power in SRAM's," IEICE Transactions on Electronics, vol. E90-C, no. 4, pp. 743-748, Apr. 2007.
  34. Y. Morita, H. Fujiwara, H. Noguchi, Y. Iguchi, K. Nii, H. Kawaguchi, and M. Yoshimoto, "Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes," IEICE Transactions on Electronics, vol. E90-C, no. 10, pp. 1949-1956, Oct. 2007.
  35. K. Onizuka, K. Inagaki, H. Kawaguchi, M. Takamiya, and T. Sakurai, "Stacked-Chip Implementation of On-Chip Buck Converter for Distributed Power Supply System in SiPs," IEEE Journal of Solid-State Circuits, vol. 42, no. 11, pp. 2404-2410, Nov. 2007.
  36. H. Kawaguchi, D. D. Antono, and T. Sakurai, "Closed-Form Expressions for Delay and Crosstalk Noise in Capacitively Coupled Distributed RC Lines," IEICE Transactions on Fundamentals, vol. E90-A, no. 12, pp. 2669-2681, Dec. 2007.
  37. Y. Morita, H. Fujiwara, H. Noguchi, Y. Iguchi, K. Nii, H. Kawaguchi, and M. Yoshimoto, "Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme," IEICE Transactions on Fundamentals, vol. E90-A, no. 12, pp. 2695-2702, Dec. 2007.
  38. T. Matsuda, M. Ichien, H. Kawaguchi, C. Ohta, and M. Yoshimoto, "Data Transmission Scheduling based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks," IEICE Transactions on Communications, vol. E90-B, no. 12, pp. 3410-3418, Dec. 2007.
  39. Y. Murachi, Y. Fukuyama, R. Yamamoto, J. Miyakoshi, H. Kawaguchi, H. Ishihara, M. Miyama, Y. Matsuda and M. Yoshimoto, "A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition," IEICE Transactions on Electronics, vol. E91-C, no. 4, pp. 457-464, Apr. 2008.
  40. Y. Murachi, J. Miyakoshi, M. Hamamoto, T. Iinuma, T. Ishihara, F. Yin, J. Lee, H. Kawaguchi, and M. Yoshimoto, "A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer," IEICE Transactions on Electronics, vol. E91-C, no. 4, pp. 465-478, Apr. 2008.
  41. H. Noguchi, Y. Iguchi, H. Fujiwara, S. Okumura, Y. Morita, K. Nii, H. Kawaguchi, and M. Yoshimoto, "A 10T Non-Precharge Two-Port SRAM Reducing Readout Power for Video Processing," IEICE Transactions on Electronics, vol. E91-C, no. 4, pp. 543-552, Apr. 2008.
  42. H. Fujiwara, K. Nii, H. Noguchi, J. Miyakoshi, Y. Murachi, Y. Morita, H. Kawaguchi, and M. Yoshimoto, "Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering," IEEE Transactions on Very Large Scale Integration Systems, vol. 16, no. 6, pp. 620-627, June 2008.
  43. T. Takeuchi, Y. Otake, M. Ichien, A. Gion, H. Kawaguchi, C. Ohta, and M. Yoshimoto, "Cross-Layer Design for Low-Power Wireless Sensor Node using Wave Clock," IEICE Transactions on Communications, vol. E91-B, no. 11, pp. 3480-3488, Nov. 2008.
  44. S. Izumi, T. Takeuchi, T. Matsuda, H. Kawaguchi, C. Ohta, and M. Yoshimoto, "Counter-Based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks," IEICE Transactions on Communications, vol. E91-B, no. 11, pp. 3489-3498, Nov. 2008.
  45. H. Fujiwara, S. Okumura, Y. Iguchi, H. Noguchi, H. Kawaguchi, and M. Yoshimoto, "A Dependable SRAM with 7T/14T Memory Cells," IEICE Transactions on Electronics, vol. E92-C, no. 4, pp. 423-432, Apr. 2009.
  46. T. Takeuchi, S. Mikami, H. Lee, H. Kawaguchi, C. Ohta, and M. Yoshimoto, "A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks," IEICE Transactions on Electronics, vol. E92-C, no. 6, pp. 815-821, June 2009.
  47. T. Matsuda, T. Takeuchi, T. Aonishi, M. Ichien, H. Kawaguchi, C. Ohta, and M. Yoshimoto, "A power-variation model for sensor node and the impact against life time of wireless sensor networks," IEICE Electronics Express, vol. 7, no. 3, pp. 197-202, Feb. 2010.
  48. S. Izumi, T. Takeuchi, T. Matsuda, H. Lee, T. Konishi, K. Tsuruda, Y. Sakai, H. Kawaguchi, C. Ohta, and M. Yoshimoto, "A 58-µW Single-Chip Sensor Node Processor with Communication Centric Design," IEICE Transactions on Electronics, vol. E93-C, no. 3, pp. 261-269, Mar. 2010.

    Conferences

  49. H. Kawaguchi, and T. Sakurai, "A Reduced Clock-Swing Flip-Flop (RCSFF) for 63% Clock Power Reduction," IEEE/JSAP Symposium on VLSI Circuits Digest of Technical Papers, pp. 97-98, June 1997.
  50. T. Sakurai, H. Kawaguchi, and T. Kuroda, "(Invited) Low-Power CMOS Design through VTH Control and Low-Swing Circuits," Proceedings of ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 1-6, Aug. 1997.
  51. H. Kawaguchi, and T. Sakurai, "Noise Expressions for Capacitance-Coupled Distributed RC Lines," Proceedings of ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 270-279, Dec. 1997.
  52. H. Kawaguchi, K. Nose, and T. Sakurai, "A CMOS Scheme for 0.5V Supply Voltage with Pico-Ampere Standby Current," IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 192-193, Feb. 1998. (Slides)
  53. H. Kawaguchi, and T. Sakurai, "Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 35-43, Feb. 1998.
  54. H. Kawaguchi, Y. Itaka, and T. Sakurai, "Dynamic Leakage Cut-off Scheme for Low-Voltage SRAM's," IEEE/JSAP Symposium on VLSI Circuits Digest of Technical Papers, pp. 140-141, June 1998.
  55. H. Kawaguchi, K. Nose, and T. Sakurai, "(Invited) A CMOS Scheme for 0.5V Supply Voltage with Pico-Ampere Standby Current," Proceedings of International Workshop on Advanced LSIs, pp. 45-49, July 1998.
  56. K. Kanda, K. Nose, H. Kawaguchi, and T. Sakurai, "Design Impact of Positive Temperature Dependence of Drain Current in Sub 1V CMOS VLSI's," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 563-566, May 1999.
  57. T. Inukai, M. Takamiya, K. Nose, H. Kawaguchi, T. Hiramoto, and T. Sakurai, "Boosted Gate MOS (BGMOS): Device/Circuit Cooperation Scheme to Achieve Leakage-Free Giga-Scale Integration," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 409-412, May 2000.
  58. T. Hiramoto, M. Takamiya, H. Koura, T. Inukai, H. Gomyo, H. Kawaguchi, and T. Sakurai, "(Invited) Optimum Device Parameters and Scalability of Variable Threshold CMOS (VTMOS)," International Conference on Solid State Devices and Materials (SSDM), pp. 372-373, Aug. 2000.
  59. K. Kanda, N. D. Minh, H. Kawaguchi, and T. Sakurai, "Abnormal Leakage Suppression (ALS) Scheme for Low Standby Current SRAMs," IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 174-175, Feb. 2001. (Slides)
  60. H. Kawaguchi, G. Zhang, S. Lee, and T. Sakurai, "An LSI for VDD-Hopping and MPEG4 System Based on the Chip," Proceedings of IEEE International Symposium on Circuit and Systems (ISCAS), pp. 918-921, May 2001.
  61. K. Nose, M. Hirabayashi, H. Kawaguchi, S. Lee, and T. Sakurai, "VTH-hopping Scheme for 82% Power Saving in Low-voltage Processors," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 93-96, May 2001.
  62. Y. Shin, H. Kawaguchi, and T. Sakurai, "Cooperative Voltage Scaling (CVS) between OS and Applications for Low-Power Real-Time Systems," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 553-556, May 2001.
  63. H. Kawaguchi, Y. Shin, and T. Sakurai, "Experimental Evaluation of Cooperative Voltage Scaling (CVS): A Case Study," Proceedings of IEEE Workshop on Power Management for Real-Time and Embedded Systems, pp. 17-23, May 2001.
  64. K. Aisaka, T. Aritsuka, S. Misaka, K. Toyama, K. Uchiyam, K. Ishibashi, H. Kawaguchi, and T. Sakurai, "Design Rule for Frequency-Voltage Cooperative Power Control and Its Application to an MPEG-4 Decoder," IEEE/JSAP Symposium on VLSI Circuits Digest of Technical Papers, pp. 216-217, June 2002.
  65. K. Kanda, T. Miyazaki, K. Min, H. Kawaguchi, and T. Sakurai, "Two Orders of Magnitude Leakage Power Reduction of Low Voltage SRAM's by Row-by-Row Dynamic VDD Control (RRDV) Scheme," Proceedings of IEEE International ASIC/SOC Conference, pp. 381-385, Sep. 2002.
  66. H. Kawaguchi, K. Kanda, K. Nose, S. Hattori, D. D. Antono, D. Yamada, T. Miyazaki, K. Inagaki, T. Hiramoto, and T. Sakurai "A 0.5-V, 400-MHz, VDD-Hopping Processor with Zero-VTH FD-SOI Technology," IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 106-107, Feb. 2003. (Slides)
  67. K. Kanda, D. D. Antono, K. Ishida, H. Kawaguchi, T. Kuroda, and T. Sakurai, "1.27-Gbps/pin, 3mW/pin Wireless Superconnect (WSC) Interface Scheme," IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 186-187, Feb. 2003. (Slides)
  68. K. Min, H. Kawaguchi, and T. Sakurai, "Zigzag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-Gating Scheme in Leakage Dominant Era," IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 400-401, Feb. 2003. (Slides)
  69. S. Misaka, K. Toyama, T. Aritsuka, K. Uchiyama, K. Aisaka, H. Kawaguchi, and T. Sakurai, "Frequency-Voltage Cooperative Power Reduction for Multi-tasking Multimedia Applications," IEEE International Symposium on Low-Power and High-Speed Chips (COOL Chips), vol. I, pp. 103-116, Apr. 2003.
  70. T. Someya, H. Kawaguchi, and T. Sakurai, "Cut-and-Paste Organic FET Customized ICs for Application to Artificial Skin," IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 288-289, Feb. 2004. (Slides)
  71. T. Sekitani, H. Kawaguchi, T. Sakurai, and T. Someya, "Organic field-effect transistors with bending radius down to 1 mm," Materials Research Society Spring Meeting (MRS), p. 173, Apr. 2004.
  72. T. Miyazaki, T. Q. Canh, H. Kawaguchi, and T. Sakurai, "Observation of one-fifth-a-clock wake-up time of power-gated circuit," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 87-90, Oct. 2004.
  73. T. Someya, T. Sakurai, T. Sekitani, H. Kawaguchi, S. Iba, and Y. Kato, "A Large-Area, Flexible, and Lightweight Sheet Image Scanner Integrated with Organic Field-Effect Transistors and Organic Photodiodes," IEEE International Electron Devices Meeting Digest of Technical Papers (IEDM), pp. 365-368, Dec. 2004.
  74. H. Kawaguchi, S. Iba, Y. Kato, T. Sekitani, T. Someya, and T. Sakurai, "A Sheet-Type Scanner Based on a 3D Stacked Organic-Transistor Circuit with Double Word-Line and Double Bit-Line Structure," IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 580-581, Feb. 2005. (Slides)
  75. S. Misaka, H. Kawaguchi, and T. Sakurai, "Time Revising Robust Frequency-Voltage Cooperative Power Reduction for Multi-tasking Multimedia Applications," IEEE International Symposium on Low-Power and High-Speed Chips (COOL Chips), pp. 165-180, Apr. 2005.
  76. T. Someya, T. Sakurai, T. Sekitani, H. Kawaguchi, S. Iba, and Y. Kato, "(Invited) Recent Advances in Applications of Organic Integrated Circuits for Large-Area Electronics," Proceedings of IEEE International Conference on IC Design and Technology (ICICDT), pp. 57-58, May 2005.
  77. C. Q. Tran, H. Kawaguchi, and T. Sakurai, "Low-power High-speed Level Shifter Design for Block-level Dynamic Voltage Scaling Environment," Proceedings of IEEE International Conference on IC Design and Technology (ICICDT), pp. 229-232, May 2005.
  78. K. Ishida, K. Kanda, A. Tamtrakarn, H. Kawaguchi, and T. Sakurai, "Subthreshold-Leakage Suppressed Switched Capacitor Circuit Based on Super Cut-Off CMOS (SCCMOS)," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3119-3122, May 2005.
  79. C. Q. Tran, H. Kawaguchi, and T. Sakurai, "More Than Two Orders of Magnitude Leakage Current Reduction in Look-Up Table for FPGA's," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 4701-4704, May 2005.
  80. K. Ishida, K. Kanda, A. Tamtrakarn, H. Kawaguchi, and T. Sakurai, "Managing Leakage in Charge-Based Analog Circuits with Low-VTH Transistors by Analog T-Switch (AT-Switch) and Super Cut-off CMOS," IEEE/JSAP Symposium on VLSI Circuits Digest of Technical Papers, pp. 122-125, June 2005.
  81. F. R. Saliba, H. Kawaguchi, and T. Sakurai, "Experimental Verification of Row-by-Row Variable VDD Scheme Reducing 95% Active Leakage Power of SRAM's," IEEE/JSAP Symposium on VLSI Circuits Digest of Technical Papers, pp. 162-165, June 2005.
  82. T. Someya, T. Sakurai, T. Sekitani, H. Kawaguchi, Y. Kato, and S. Iba, "(Invited) A Sheet Image Scanner Based on 3D-Stacked Organic Transistor Integrated Circuits," International Workshop on Active-Matrix Liquid-Crystal Displays, pp. 87-90, July 2005.
  83. T. Someya, T. Sakurai, T. Sekitani, H. Kawaguchi, S. Iba, Y. Kato, and Y. Noguchi, "(Invited) Recent Progress of Organic Transistor Integrated Circuits for Large-Area Sensor Applications," Proceedings of International Conference on Solid State Devices and Materials (SSDM), pp. 380-381, Sep. 2005.
  84. T. Someya, T. Sakurai, T. Sekitani, H. Kawaguchi, Y. Kato, and S. Iba, "(Invited) Pocket scanner using organic transistors and detectors," Proceeding of Annual Meeting of the IEEE Lasers and Electro-Optics Society, pp. 59-60, Oct. 2005.
  85. C. Q. Tran, H. Kawaguchi, and T. Sakurai, "95% Leakage-Reduced FPGA using Zigzag Power-gating, Dual-VTH/VDD and Micro-VDD-Hopping," IEEE Asian Solid-State Circuits Conference Proceedings of Technical Papers (A-SSCC), pp. 149-152, Nov. 2005.
  86. Y. Kato, S. Iba, T. Sekitani, Y. Noguchi, K. Hizu, X. Wang, K. Takenoshita, Y. Takamatsu, S. Nakano, K. Fukuda, K. Nakamura, T. Yamaue, M. Doi, K. Asaka, H. Kawaguchi, M. Takamiya, T. Sakurai, and T. Someya, "A Flexible, Lightweight Braille Sheet Display with Plastic Actuators Driven by An Organic Field-Effect Transistor Active Matrix," IEEE International Electron Devices Meeting Digest of Technical Papers (IEDM), pp. 105-108, Dec. 2005.
  87. T. Someya, T. Sakurai, T. Sekitani, H. Kawaguchi, Y. Kato, and S. Iba, "(Invited) Sheet Image Scanner with Organic Transistor Integrated Circuits," Proceedings of International Display Workshops (IDW), pp. 1037-1040, Dec. 2005.
  88. M. Takamiya, T. Sekitani, Y. Kato, H. Kawaguchi, T. Someya, and T. Sakurai, "An Organic FET SRAM for Braille Sheet Display with Back Gate to Increase Static Noise Margin," IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 276-277, Feb. 2006. (Slides)
  89. R. Yamamoto, Y. Fukuyama, T. Katagiri, J. Miyakoshi, Y. Kuroda, N. Minegishi, M. Miyama, H. Kawaguchi, K. Imamura, H. Hashimoto, and M. Yoshimoto, "An Architecture Study of Scalable Optical-Flow Processor for Real-Time Video Segmentation," IEEE International Symposium on Low-Power and High-Speed Chips (COOL Chips), pp. 225-240, Apr. 2006.
  90. M. Takamiya, T. Sekitani, Y. Kato, H. Kawaguchi, T. Someya, and T. Sakurai, "(Invited) Low Power and Flexible Braille Sheet Display with Organic FET's and Plastic Actuators," Proceedings of IEEE International Conference on IC Design and Technology (ICICDT), pp. 1-4, May 2006.
  91. Y. Morita, H. Fujiwara, H. Noguchi, K. Kawakami, J. Miyakoshi, S. Mikami, K. Nii, H. Kawaguchi, and M. Yoshimoto, "A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC under DVS Environment," IEEE/JSAP Symposium on VLSI Circuits Digest of Technical Papers, pp. 16-17, June 2006.
  92. T. Aonishi, T. Matsuda, S. Mikami, H. Kawaguchi, C. Ohta, and M. Yoshimoto, "Impact of Aggregation Efficiency on GIT Routing for Wireless Sensor Networks," Proceedings of International Workshop on Wireless and Sensor Networks (WSNet), pp. 151-158, Aug. 2006.
  93. K. Onizuka, H. Kawaguchi, M. Takamiya, T. Kuroda, and T. Sakurai, "Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 575-578, Sep. 2006.
  94. H. Fujiwara, K. Nii, J. Miyakoshi, Y. Murachi, Y. Morita, H. Kawaguchi, and M. Yoshimoto, "A Two-Port SRAM for Real-Time Video Processor Saving 53% of Bitline Power with Majority Logic and Data-Bit Reordering," Proceedings of ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 61-66, Oct. 2006.
  95. T. Matsuda, T. Takeuchi, H. Yoshino, M. Ichien, S. Mikami, H. Kawaguchi, C. Ohta, and M. Yoshimoto, "A Power-Variation Model for Sensor Node and the Impact against Life Time of Wireless Sensor Networks," Proceedings of International Conference on Communications and Electronics (ICCE), pp. 106-111, Oct. 2006.
  96. M. Ichien, T. Takeuchi, S. Mikami, H. Kawaguchi, C. Ohta, and M. Yoshimoto, "Isochronous MAC using Long-Wave Standard Time Code for Wireless Sensor Networks," Proceedings of International Conference on Communications and Electronics (ICCE), pp. 172-177, Oct. 2006.
  97. T. Matsuda, M. Ichien, S. Mikami, H. Kawaguchi, C. Ohta, and M. Yoshimoto, "Data Transmission Scheduling based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks," Proceedings of International Conference on Communications and Electronics (ICCE), CD-ROM, Oct. 2006.
  98. J. Miyakoshi, Y. Murachi, T. Matsuno, M. Hamamoto, T. Iinuma, T. Ishihara, H. Kawaguchi, and M. Yoshimoto, "A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing," Proceedings of IFIP International Conference on Very Large Scale Integration (VLSI-SoC), pp. 192-197, Oct. 2006.
  99. T. Iinuma, J. Miyakoshi, Y. Murachi, T. Matsuno, M. Hamamoto, T. Ishihara, H. Kawaguchi, M. Yoshimoto, and M. Miyama, "An 800-µW H.264 Baseline-Profile Motion Estimation Processor Core," IEEE Asian Solid-State Circuits Conference Proceedings of Technical Papers (A-SSCC), pp. 99-102, Nov. 2006.
  100. K. Onizuka, H. Kawaguchi, M. Takamiya, and T. Sakurai, "Stacked-Chip Implementation of On-Chip Buck Converter for Power-Aware Distributed Power Supply Systems," IEEE Asian Solid-State Circuits Conference Proceedings of Technical Papers (A-SSCC), pp. 127-130, Nov. 2006.
  101. T. Sekitani, M. Takamiya, Y. Noguchi, S. Nakano, Y. Kato, K. Hizu, H. Kawaguchi, T. Sakurai, and T. Someya, "A Large-area Flexible Wireless Power Transmission Sheet Using Printed Plastic MEMS Switches and Organic Field-effect Transistors," IEEE International Electron Devices Meeting Digest of Technical Papers (IEDM), pp. 287-290, Dec. 2006.
  102. M. Takamiya, T. Sekitani, Y. Kato, H. Kawaguchi, T. Someya, and T. Sakurai, "(Invited) Flexible Braille Sheet Display with Organic FETs and Plastic Actuators," Proceedings of International Display Workshops (IDW), pp. 261-264, Dec. 2006.
  103. S. Mikami, T. Takeuchi, T. Matsuda, H. Kawaguchi, C. Ohta, and M. Yoshimoto, "An Efficiency Degradation Model of Power Amplifier and the Impact against Transmission Power Control for Wireless Sensor Networks," Proceedings of IEEE Radio and Wireless Symposium (RWS), pp. 447-450, Jan. 2007.
  104. S. Mikami, M. Ichien, T. Takeuchi, H. Kawaguchi, C. Ohta, and M. Yoshimoto, "A 356-µW, 433-MHz, Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks," Proceedings of IEEE Radio and Wireless Symposium (RWS), pp, 451-454, Jan. 2007.
  105. K. Kawakami, J. Takemura, M. Kuroda, H. Kawaguchi, and M. Yoshimoto, "Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 292-297, Jan. 2007.
  106. M. Takamiya, T. Sekitani, Y. Miyamoto, Y. Noguchi, H. Kawaguchi, T. Someya, and T. Sakurai, "Design Solutions for a Multi-Object Wireless Power Transmission Sheet Based on Plastic Switches," IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 362-363, Feb. 2007.
  107. H. Noguchi, Y. Iguchi, H. Fujiwara, Y. Morita, K. Nii, H. Kawaguchi, and M. Yoshimoto, "A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing," Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 107-112, May 2007.
  108. K. Onizuka, M. Takamiya, H. Kawaguchi, and T. Sakurai, "(Invited) A Design Methodology of Chip-to-Chip Wireless Power Transmission System," Proceedings of IEEE International Conference on IC Design and Technology (ICICDT), pp. 143-146, May 2007.
  109. M. Takamiya, T. Sekitani, Y. Miyamoto, Y. Noguchi, H. Kawaguchi, T. Someya, and T. Sakurai, "(Invited) Design for Mixed Circuits of Organic FETs and Plastic MEMS Switches for Wireless Power Transmission Sheet," Proceedings of IEEE International Conference on IC Design and Technology (ICICDT), pp. 168-171, May 2007.
  110. Y. Morita, H. Fujiwara, H. Noguchi, Y. Iguchi, K. Nii, H. Kawaguchi, and M. Yoshimoto, "An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment," IEEE/JSAP Symposium on VLSI Circuits Digest of Technical Papers, pp. 256-257, June 2007.
  111. D. Levacq, M. Yazid, H. Kawaguchi, M. Takamiya, and T. Sakurai, "Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution," Proceedings of European Solid-State Circuits Conference (ESSCIRC), pp. 190-193, Sep. 2007.
  112. Y. Sakata, K. Kawakami, H. Kawaguchi, and M. Yoshimoto, "An Elastic Pipeline Architecture for Dynamic Voltage Scaling and Its Application to Low-Power Portable H.264/AVC Decoder with Embedded Frame Buffer SRAM," Proceedings of WSEAS European Computing Conference (ECC), pp. 883-890, Sep. 2007. (In press)
  113. S. Izumi, T. Matsuda, H. Kawaguchi, C. Ohta, and M. Yoshimoto, "Improvement of Counter-based Broadcasting by Random Assessment Delay Extension for Wireless Sensor Networks," Proceedings of IARIA International Conference on Sensor Technologies and Applications (SENSORCOMM), pp. 76-81, Oct. 2007.
  114. Y. Otake, M. Ichien, T. Takeuchi, A. Gion, S. Mikami, H. Fujiwara, H. Kawaguchi, C. Ohta, and M. Yoshimoto, "Cross-Layer Design for Low-Power Wireless Sensor Node using Long-Wave Standard Time Code," Proceedings of IARIA International Conference on Sensor Technologies and Applications (SENSORCOMM), pp.341-346, Oct. 2007.
  115. T. Matsuda, T. Aonishi, T. Takeuchi, H. Kawaguchi, C. Ohta, and M. Yoshimoto, "Multipath Routing using Isochronous Medium Access Control with Multi Wakeup Period for Wireless Sensor Networks," Proceedings of IEEE International Symposium on Wireless Communication Systems (ISWCS), pp. 718-721, Oct. 2007.
  116. H. Ishihara, M. Miyama, Y. Matsuda, Y. Murachi, Y. Fukuyama, R. Yamamoto, J. Miyakoshi, H. Kawaguchi, M. Yoshimoto, "A VGA 30-fps Optical-Flow Processor Core Based on Pyramidal Lucas and Kanade Algorithm," IEEE Asian Solid-State Circuits Conference Proceedings of Technical Papers (A-SSCC), pp. 188-191, Nov. 2007.
  117. M. Takamiya, T. Sekitani, Y. Miyamoto, Y. Noguchi, H. Kawaguchi, T. Someya, and T. Sakurai, "(Invited) Wireless Power Transmission Sheet with Organic FETs and Plastic MEMS Switches," Proceedings of International Display Workshops (IDW), pp. 95-98, Dec. 2007.
  118. T. Ishihara, Y. Murachi, T. Iinuma, F. Yin, T. Kamino, K. Mizuno, H. Kawaguchi, and M. Yoshimoto, "A Sub-100mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for Real-time MBAFF Encoding," IEEE International Solid-State Circuits Conference Student Forum, Feb. 2008.
  119. H. Fujiwara, S. Okumura, Y. Iguchi, H. Noguchi, Y. Morita, H. Kawaguchi, and M. Yoshimoto, "Quality of a Bit (QoB): A New Concept in Dependable SRAM," Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), pp. 98-102, Mar. 2008.
  120. S. Izumi, T. Matsuda, H. Kawaguchi, C. Ohta, and M. Yoshimoto, "Hop Count Aware Broadcast Algorithm with Random Assessment Delay Extension for Wireless Sensor Networks," Proceedings of IEEE/IEICE Asia-Pacific Symposium on Information and Telecommunication Technologies (APSITT), pp. 30-35, Apr. 2008.
  121. T. Matsuda, S. Izumi, T. Takeuchi, H. Fujiwara, H. Kawaguchi, C. Ohta, and M. Yoshimoto, "Impact of Random Access Memory aware Data Aggregation for Wireless Sensor Network," Proceedings of IEEE/IEICE Asia-Pacific Symposium on Information and Telecommunication Technologies (APSITT), pp. 130-134, Apr. 2008.
  122. Y. Murachi, T. Kamino, J. Miyakoshi, H. Kawaguchi, and M. Yoshimoto, "A Power-Efficient SRAM Core Architecture with Segmentation-Free and Rectangular Accessibility for Super-Parallel Video Processing," Proceedings of IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 63-66, Apr. 2008.
  123. Y. Murachi, K. Mizuno, J. Miyakoshi, M. Hamamoto, T. Iinuma, T. Ishihara, F. Yin, J. Lee, T. Kamino, H. Kawaguchi, and M. Yoshimoto, "A Sub 100 mW H.264/AVC MP@L4.1 Integer-Pel Motion Estimation Processor VLSI for MBAFF Encoding," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)C pp. 848-851, May 2008.
  124. H. Noguchi, S. Okumura, Y. Iguchi, H. Fujiwara, Y. Morita, K. Nii, H. Kawaguchi, and M. Yoshimoto, "Which is the Best Dual-Port SRAM in 45-nm Process Technology? - 8T, 10T Single End, and 10T Differential -," Proceedings of IEEE International Conference on IC Design and Technology (ICICDT), pp.55-58, June 2008.
  125. K. Mizuno, J. Miyakoshi, Y. Murachi, M. Hamamoto, T. Iinuma, T. Ishihara, F. Yin, J. Lee, H. Kawaguchi, and M. Yoshimoto, "An H.264/AVC MP@L4.1 Quarter-Pel Motion Estimation Processor VLSI for Real-Time MBAFF Encoding," Proceedings of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 1179-1182, Sep. 2008.
  126. H. Fujiwara, T. Takeuchi, Y. Otake, M. Yoshimoto, and H. Kawaguchi, "An Inter-Die Variability Compensation Scheme for 0.42-V 486-kb FD-SOI SRAM using Substrate Control," Proceedings of IEEE International SOI Conference, pp. 93-94, Oct. 2008.
  127. K. Miura, H. Noguchi, H. Kawaguchi, and M. Yoshimoto, "A Low Memory Bandwidth Gaussian Mixture Model (GMM) Processor for 20,000-Word Real-Time Speech Recognition FPGA System," Proceedings of IEEE International Conference on Field-Programmable Technology (FPT), pp. 341-344, Dec. 2008.
  128. K. Tsuruda, S. Izumi, H. Lee, T. Takeuchi, H. Kawaguchi, and M. Yoshimoto, "A Flexible Baseband Processor with Multi-Resolution Spectrum-Sensing Functionality," Proceedings of IEEE/IEICE International Symposium on Information Theory and its Applications (ISITA), pp. 1423-1428, Dec. 2008.
  129. H. Fujiwara, S. Okumura, Y. Iguchi, H. Noguchi, H. Kawaguchi, and M. Yoshimoto, "A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection," Proceedings of IEEE International Conference on VLSI Design, pp. 295-300, Jan. 2009.
  130. S. Okumura, Y. Iguchi, S. Yoshimoto, H. Fujiwara, H. Noguchi, K. Nii, H. Kawaguchi, and M. Yoshimoto, "A 0.56-V 128kb 10T SRAM Using Column Line Assist (CLA) Scheme," Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), pp. 659-663, Mar. 2009.
  131. T. Takeuchi, S. Izumi, T. Matsuda, H. Lee, Y. Otake, T. Konishi, K. Tsuruda, Y. Sakai, H. Fujiwara, C. Ohta, H. Kawaguchi, and M. Yoshimoto, "A 58-uW Single-Chip Sensor Node Processor Using Synchronous MAC Protocol," IEEE/JSAP Symposium on VLSI Circuits Digest of Technical Papers, pp. 290-291, June 2009.
  132. H. Kawaguchi, "(Invited) Low-Power Control Techniques for Silicon and Organic Circuits with Array Structures," Proceedings of IEEE Conference on Control Applications (CCA), pp. 326-333, July 2009.
  133. T. Konishi, K. Tsuruda, S. Izumi, H. Lee, H. Fujiwara, T. Takeuchi, H. Kawaguchi, and M. Yoshimoto, "A 60-dB Image Rejection Filter Using - Modulation and Frequency Shifting," Proceedings of IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), pp. 565-570, Aug. 2009.
  134. T. Fujinaga, K. Miura, H. Noguchi, H. Kawaguchi, and M. Yoshimoto, "Parallelized Viterbi Processor for 5,000-Word Large-Vocabulary Real-Time Continuous Speech Recognition FPGA System," Proceedings of ISCA Annual Conference of International Speech Communication Association (Interspeech), pp.1483-1486, Sep. 2009.
  135. H. Noguchi, T. Takagi, M. Yoshimoto, and H. Kawaguchi, "An Ultra-Low-Power VAD Hardware Implementation for Intelligent Ubiquitous Sensor Networks," Proceedings of IEEE Workshop on Signal Processing Systems (SiPS), pp. 214-219, Oct. 2009.
  136. T. Takeuchi, S. Izumi, T. Matsuda, H. Lee, T. Konishi, K. Tsuruda, Y. Sakai, H. Kawaguchi, and M. Yoshimoto, "A Single-Chip Sensor Node LSI with Synchronous MAC Protocol and Divided Data-Buffer SRAM," Proceedings of IEEE International SoC Design Conference, Nov. 2009. (To appear)
  137. Y. Shimai, J. Tani, H. Noguchi, H. Kawaguchi, and M. Yoshimoto, "FPGA Implementation of Mixed Integer Quadratic Programming Solver for Mobile Robot Control," Proceedings of IEEE International Conference on Field-Programmable Technology (FPT), pp. 447-450, Dec. 2009.
  138. T. Takagi, H. Noguchi, K. Kugata, M. Yoshimoto, and H. Kawaguchi, "Microphone Array Network for Ubiquitous Sound Acquisition," Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp. 1474-1477, Mar. 2010.
  139. K. Kugata, T. Takagi, H. Noguchi, M. Yoshimoto, and H. Kawaguchi, "Intelligent Ubiquitous Sensor Network for Sound Acquisition," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1414-1417, May 2010.
  140. K. Kugata, T. Takagi, H. Noguchi, M. Yoshimoto, and H. Kawaguchi, "Intelligent Ubiquitous Sensor Network for Sound Acquisition," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1414-1417, May 2010.
  141. H. Noguchi, T. Takagi, K. Kugata, M. Yoshimoto, and H. Kawaguchi, "Low-Traffic and Low-Power Data-Intensive Sound Acquisition with Perfect Aggregation Specialized for Microphone Array Networks," Proceedings of IARIA International Conference on Sensor Technologies and Applications (SENSORCOMM), July 2010 (To be presented).

    Books

  142. T. Sakurai, A. Matsuzawa, and T. Douseki, "Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-power Applications," ISBN-10 0-387-29217-9, Springer, Apr. 2006. (H. Kawaguchi, Section 4.7, pp. 196-207)

    Awards

  143. T. Someya, H. Kawaguchi, and T. Sakurai, "Cut-and-Paste Organic FET Customized ICs for Application to Artificial Skin," IEEE International Solid-State Circuits Conference (ISSCC) 2004 Takuo Sugano Outstanding Paper Award, Feb. 7, 2005.
  144. S. Mikami, T. Takeuchi, T. Matsuda, H. Kawaguchi, C. Ohta, and M. Yoshimoto, "An Efficiency Degradation Model of Power Amplifier and the Impact against Transmission Power Control for Wireless Sensor Networks," IEEE Radio and Wireless Symposium (RWS) 2007 Best Student Paper Award (Nominated), Jan. 10, 2007.
  145. H. Kawaguchi, IEEE Kansai Section 2006 Gold Award, Feb. 6, 2007.
  146. Y. Otake, M. Ichien, T. Takeuchi, A. Gion, S. Mikami, H. Fujiwara, H. Kawaguchi, C. Ohta, and M. Yoshimoto, "Cross-Layer Design for Low-Power Wireless Sensor Node using Long-Wave Standard Time Code," IARIA International Conference on Sensor Technologies and Applications (SENSORCOMM) 2007 Best Paper Award, Dec. 10, 2007.
  147. S. Okumura, Y. Iguchi, S. Yoshimoto, H. Fujiwara, H. Noguchi, K. Nii, H. Kawaguchi, and M. Yoshimoto, "A 0.56-V 128kb 10T SRAM Using Column Line Assist (CLA) Scheme," IEEE International Symposium on Quality Electronic Design (ISQED) 2009 Best Paper Award (Nominated), Mar. 17, 2009.

    Academic activities

  148. A Member of the Institute of Electrical and Electronics Engineers (IEEE), Jan. 1998 -.
  149. A Member of Association for Computing Machinery (ACM), Nov. 1999 -.
  150. A Program Committee Member for IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips), July 2005 -.
  151. An Associate Editor of IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Aug. 2005 -.
  152. An Organizing Committee Publicity for IEEE Asian Solid-State Circuits Conference (A-SSCC), Jan. 2008 - Nov. 2008.
  153. A University Design Contest Committee Member for Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2008 -.
  154. A Secretary for IEEE Solid-State Circuits Society Kansai Chapter, Jan. 2009 - Dec. 2010.
  155. A University Design Contest Committee Chair for Asia and South Pacific Design Automation Conference (ASP-DAC), Apr. 2009 -.
  156. A Technical Program Committee Member for IEEE Custom Integrated Circuits Conference (CICC), Feb. 2010 -.
  157. An Associate Editor of IPSJ Transactions on System LSI Design Methodology (TSLDM), Apr. 2010 - Mar. 2012.